MT46V16M8TG-8 データシートの表示（PDF） - Micron Technology

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MT46V16M8TG-8

DOUBLE DATA RATE (DDR) SDRAM

Micron Technology 

T1

CK#

CK

tHP5

DQS1

QFC#

DQ (Last data valid)

DQ2

DQ2

DQ2

DQ2

DQ2

DQ2

DQ (First data no longer valid)

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

T2

T2n

T3

T3n

T4

tHP5

tHP5

tHP5

tDQSQ3

tDQSQ3

tHP5

tDQSQ3

tHP5

tDQSQ3

tQH4

tQH4

tQH4

tQH4

DQ (Last data valid)

DQ (First data no longer valid)

T2

T2n

T3

T3n

T2

T2n

T3

T3n

All DQs and DQS, collectively6

T2

T2n

T3

T3n

Earliest signal transition

Latest signal transition

Data

Valid

window

Data

Valid

window

Data

Valid

window

Data

Valid

window

NOTE: 1. DQs transitioning after DQS transition define tDQSQ window. DQS transitions at T2 and at T2n are an “early DQS,”

at T3 is a “nominal DQS,” and at T3n is a "late DQS"

2. For a x4, only two DQs apply.

3. tDQSQ is derived at each DQS clock edge and is not cumulative over time and begins with DQS transition and

ends with the last valid transition of DQs .

4. tQH is derived from tHP : tQH = tHP - tQHS.

5. tHP is the lesser of tCL or tCH clock transition collectively when a bank is active.

6. The data valid window is derived for each DQS transitions and is defined as tQH minus tDQSQ.

Figure 29 – x4, x8

Data Output Timing – tDQSQ, tQH and Data Valid Window

128Mb: x4, x8, x16 DDR SDRAM

128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01

56

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2001, Micron Technology, Inc.

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