FW21555BA データシートの表示（PDF） - Intel

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FW21555BA

Non-Transparent PCI-to-PCI Bridge

Intel 

Non-Transparent PPB

1.2

Architectural Overview

The 21555 consists of the following function blocks:

Data Buffers

Data buffers include the buffers along with the associated data path control logic. Delayed

transaction buffers contain the compare functionality for completing delayed transactions. The

blocks also contain the watchdog timers associated with the buffers. The data buffers are as

follows:

• Four-entry downstream delayed transaction buffer

• Four-entry upstream delayed transaction buffer

• 256-byte downstream posted write buffer

• 256-byte upstream posted write buffer

• 256-byte downstream read data buffer

• 256-byte upstream read data buffer

• Two downstream I2O delayed transaction entries

Registers

The following register blocks also contain address decode and translation logic, I2O message unit,

and interrupt control logic:

• Primary interface header Type 0 configuration registers

• Secondary interface header Type 0 configuration registers

• Device-specific configuration registers

• Memory and I/O mapped control and status registers

Control Logic

The 21555 has the following control logic:

• Primary PCI target control logic

• Primary PCI master control logic

• Secondary PCI target control logic

• Secondary PCI master control logic

• ROM interface control logic for both serial and parallel ROM connections (interfaces between

the ROM registers and ROM signals)

• Secondary PCI bus arbiter interface to secondary bus device request and grant lines, as well as

the 21555 secondary master control logic

• JTAG control logic

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Datasheet

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