MC35XS3500DHFK データシートの表示（PDF） - Freescale Semiconductor

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MC35XS3500DHFK

Smart Rear Corner Light Switch (Penta 35 mOhm)

Freescale Semiconductor 

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 5. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 4.5 V  VCC  5.5 V, 7.0 V  VBAT  20 V, -40C  TA  125C, unless otherwise noted.

Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

PWM MODULE

Nominal PWM Frequency Range(43)

f PWM

30

–

400

Hz

Clock Input Frequency Range

f CLK

7.68

–

51.2

kHz

Output PWM Duty Cycle maximum range for 11 V<VBAT<18 V(41), (43)

PWM_MAX

4.0

–

96

%

Output PWM Duty Cycle linear range for 11 V<VBAT<18 V(42), (43)

PWM_LIN

5.5

–

96

%

Output PWM Duty Cycle range for full diagnostic for 11 V<VBAT<18 V(44)

PWM_DIAG

%

200 Hz Output PWM frequency

5.5

–

96

400 Hz Output PWM frequency

11

–

90

WATCHDOG TIMING

Watchdog Timeout (SPI Failure)

I /O PLAUSIBILITY CHECK TIMING

t WDTO

50

75

100

ms

Fault Shutdown Delay Time (from Over-temperature or OCHI1 or OHCI2 or

t SD

OCLO Fault Detection to Output = 50% VBAT without round shaping feature

for turn off)

–

7.0

30

s

Under-voltage Deglitch Time(45)

t UV

0.8

1.25

2.0

s

High Over-current Threshold Time 1

t1

7.0

10

13.5

ms

High Over-current Threshold Time 2

t2

52.5

75

97.5

ms

Autorestart Period

tAUTORST

52.5

75

97.5

ms

Autorestart Over-current Shutdown Delay Time

t OCSH_AUTO

3.5

5.0

6.5

ms

Limp Home Input pin Deglicher Time

t LIMP

7.0

10.0

13.0

ms

Cyclic Open Load Detection Timing with LED(46)

t OLLED

105

150

195

ms

Flasher Toggle Timeout

t FLASHER

1.4

2.3

3.0

s

Ignition Toggle Timeout

Stop Toggle Timeout

t IGNITION

1.4

2.3

3.0

s

tSTOP

1.4

2.3

3.0

s

Clock Input Low Frequency Detection Range

f LCLK DET

1.0

2.0

4.0

kHz

Clock Input High Frequency Detection Range

f HCLK DET

100

200

400

kHz

Notes

41. The PWM ratio is measured at VOUT = 50% of VBAT in nominal range of frequency. It is possible to put the device fully on (PWM duty

cycle = 100%) and fully off (PWN duty cycle = 0%). Between 4%-96%, OCLO1,2, OCLO and open load are available in ON state. See

Input Timing Switching Characteristics on page 20.

42. Linear range is defined by output duty cycle to SPI duty cycle configuration +/- LSB. For values outside the linear duty cycle range, a

calibration curve is available.

43. Not production tested.

44. Full diagnostic corresponds to the availability of the following features: output current sensing, output status and openload detection.

Not production tested.

45. This time is measured from the VBAT(UV) level to the fault reporting. Parameter guaranteed in testmode.

46. OLLEDn bit (where “n” corresponds to respective outputs 1 through 5) in SI data is set to logic [1]. Refer to Table 9, Serial Input Address

and Configuration Bit Map.

35XS3500

18

Analog Integrated Circuit Device Data

Freescale Semiconductor

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