GS881E18AT-250 データシートの表示（PDF） - Giga Semiconductor

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GS881E18AT-250

512K x 18, 256K x 36 9Mb Sync Burst SRAMs

Giga Semiconductor 

Preliminary

GS881E18/36AT-250/225/200/166/150/133

GS881E18/36A Boundary Scan Chain Order

Order

117

118

119

120

121

x36

x18

A2

A1

A0

PH = 0

G

Pin

x36 x18

35

36

37

n/a

86

Notes:

1. Depending on the package, some input pads of the scan chain may not be connected to any external pin.

In such case: LBO = 1, ZQ = 1, PE = 0, SD = 0, ZZ = 0, FT = 1, DP = 1, and SCD = 1.

2. Every DQ pad consists of two scan registers—D is for input capture, and Q is for output capture.

3. A single register (#121) for controlling tristate of all the DQ pins is at the end of the scan chain (i.e., the

last bit shifted in this tristate control is effective after JTAG EXTEST instruction is executed.

4. 1 = no connect, internally set to logic value 1

5. 0 = no connect, internally set to logic value 0

6. X = no connect, value is undefined

Rev: 1.01 3/2002

31/34

© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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