74HC4024DB(2004) データシートの表示（PDF） - Philips Electronics
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74HC4024DB Datasheet PDF : 18 Pages
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Philips Semiconductors
74HC4024
7-stage binary ripple counter
Table 8: Dynamic characteristics …continued
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 7.
Symbol Parameter
Conditions
Tamb = −40 °C to +125 °C
tPHL, tPLH propagation delay CP to Q0
propagation delay Qn to Qn+1
see Figure 6
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 6
tPHL
propagation delay MR to Q0
tTHL, tTLH output transition time
tW
CP clock pulse width HIGH or
LOW
MR master reset pulse width
HIGH
trem
removal time MR to CP
fmax
maximum clock frequency
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 6
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 6
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 6
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 6
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 6
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 6
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(CL × VCC2 × fo) = sum of outputs.
9397 750 13813
Product data sheet
Rev. 03 — 12 November 2004
Min
Typ
Max
Unit
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
120
-
24
-
20
-
120
-
24
-
20
-
75
-
15
-
13
-
4.0
-
20
-
24
-
265
ns
53
ns
45
ns
120
ns
24
ns
20
ns
300
ns
60
ns
51
ns
110
ns
22
ns
19
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
MHz
-
MHz
-
MHz
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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