74LVQ174 データシートの表示（PDF） - STMicroelectronics
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74LVQ174 Datasheet PDF : 13 Pages
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74LVQ174
Figure 2: Input And Output Equivalent Circuit
Table 2: Pin Description
PIN N°
1
2, 5, 7, 10,
12, 15
3, 4, 6, 11,
13, 14
9
8
16
SYMBOL
CLR
Q0 to Q5
NAME AND FUNCTION
Asynchronous Master
Reset (Active LOW)
Flip-Flop Outputs
D0 to D5 Data Inputs
CLK
GND
VCC
Clock Input (Positive Edge
Triggered)
Ground (0V)
Positive Supply Voltage
Table 3: Truth Table
CLR
L
H
H
H
INPUTS
D
X
L
H
X
X : Don’t Care
Figure 3: Logic Diagram
CLK
X
OUTPUT
Q
L
L
H
Qn
FUNCTION
CLEAR
NO CHANGE
This logic diagram has not to be used to estimate propagation delays
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