VG26S18165C データシートの表示（PDF） - Vanguard International Semiconductor
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VG26S18165C Datasheet PDF : 26 Pages
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VG26(V)(S)18165C/VG26(V)(S)18165D
1,048,576 x 16 - Bit
CMOS Dynamic RAM
TRUTH TABLE
FUNCTION
STANDBY
READ : WORD
READ : LOWER BYTE
RAS
H
L
L
READ: UPPER BYTE
L
WRITE: WORD
L
(EARLY WRITE)
WRITE: LOWER
L
BYTE (EARLY)
WRITE : UPPER
L
BYTE (EARLY)
READ WRITE
L
PAGE-MODE 1st Cycle
L
READ
2nd Cycle
L
PAGE-MODE 1st Cycle
L
WRITE
2nd Cycle
L
PAGE-MODE 1st Cycle
L
READ-
WRITE
2nd Cycle
L
HIDDEN
REFRESH
READ
WRITE
RAS-ONLY REFRESH
CBR REFRESH
L→H→L
L→H→L
L
H→L
LCAS
H→X
L
L
H
L
L
H
L
H→L
H→L
H→L
H→L
H→L
H→L
L
L
H
L
UCAS WE
OE
H→X
X
X
L
H
L
H
H
L
L
H
L
L
L
X
H
L
X
L
L
X
L
H→L
H→L
H→L
H→L
H→L L→H
H
L
H
L
L
X
L
X
H→L H→L L→H
H→L
L
H→L L→H
H
L
L
L
X
H
X
X
L
H
X
ADDRESSES
ROW COL
DQS
X
X High-Z
Notes
ROW
ROW
ROW
ROW
COL Data-Out
COL Lower Byte: Data-Out
Upper Byte: High-Z
COL Lower Byte: High-Z
Upper Byte: Data-Out
COL Data-In
ROW
COL Lower Byte: Data-In
Upper Byte: High-Z
ROW
COL Lower Byte: High-Z
Upper Byte: Data-In
ROW COL Data-Out, Data-In
1,2
ROW COL Data-Out
2
n/a
COL Data-Out
2
ROW COL Data-In
1
n/a
COL Data-In
1
ROW COL Data-Out, Data-In
1,2
n/a
COL Data-Out, Data-In
1,2
ROW COL Data-Out
2
ROW COL Data-In
1,3
ROW n/a High-Z
X
X High-Z
4
Notes: 1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).
2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).
3. EARLY WRITE only.
4. At least one of the two CAS signals must be active (LCAS or UCAS).
Document:1G5-0179
Rev.1
Page 4
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