VG26V18165DT-5 データシートの表示（PDF） - Vanguard International Semiconductor
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VG26V18165DT-5 Datasheet PDF : 26 Pages
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VG26(V)(S)18165C/VG26(V)(S)18165D
1,048,576 x 16 - Bit
CMOS Dynamic RAM
Read Cycle
Parameter
Symbol
Access time from RAS
Access time from LCAS / UCAS
Access time from column address
Access time from OE
Read command setup time
Read command hold time to LCAS / UCAS
Read command hold time to RAS
Output buffer turn-off time
Output buffer turn-off time from OE
tRAC
tCAC
tAA
tOEA
tRCS
tRCH
tRRH
tOFF
tOEZ
VG26(V)(S)18165
-5
-6
Unit
Min
Max
Min
Max
-
50
-
60 ns
-
13
-
15 ns
-
25
-
30 ns
-
12
-
15 ns
0
-
0
- ns
0
-
0
- ns
10
-
10
- ns
0
12
0
15 ns
0
12
0
15 ns
Notes
13
14, 15
15, 16
8
11, 17
17
18
18
Write Cycle
Parameter
Symbol
Write command setup time
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to LCAS / UCAS lead time
Data-in setup time
Data-in hold time
WE to Data-in delay
tWCS
tWCH
tWP
tRWL
tCWL
tDS
tDH
tWED
VG26(V)(S)18165
Unit
-5
-6
Min
Max
Min
Max
0
-
0
- ns
8
-
10
- ns
8
-
10
- ns
13
-
15
- ns
8
-
10
- ns
0
-
0
- ns
8
-
10
- ns
10
-
10
- ns
Notes
8, 19
20
21
21
Read- Modify- Write Cycle
Parameter
Read-modify- write cycle time
RAS to WE delay time
LCAS / UCAS to WE dealy time
Column address to WE delay time
OE hold time from WE
Symbol
tRWC
tRWD
tCWD
tAWD
tOEH
VG26(V)(S)18165
-5
Min
Max
108
-
-6
Unit
Min
Max
133
- ns
64
-
77
- ns
26
-
32
- ns
39
-
47
- ns
8
-
10
- ns
Notes
19
19
19
Document:1G5-0179
Rev.1
Page 9
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