AD5110BCPZ10-RL7 データシートの表示（PDF） - Analog Devices

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AD5110BCPZ10-RL7

Single-Channel, 128-/64-/32-Position, I2C, ±8% Resistor Tolerance, Nonvolatile Digital Potentiometer

Analog Devices 

Data Sheet

AD5110/AD5112/AD5114

INTERFACE TIMING SPECIFICATIONS

VLOGIC = 1.8 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.

Table 5.

Parameter1

fSCL2

t1

t2

t3

t4

t5

t6

t7

Test Conditions/

Comments

Min

Standard mode

Fast mode

Standard mode 4.0

Fast mode

0.6

Standard mode 4.7

Fast mode

1.3

Standard mode 250

Fast mode

100

Standard mode 0

Fast mode

0

Standard mode 4.7

Fast mode

0.6

Standard mode 4

Fast mode

0.6

Standard mode 4.7

Typ Max

100

400

3.45

0.9

Fast mode

1.3

t8

Standard mode 4

Fast mode

0.6

t9

Standard mode

Fast mode

20 + 0.1 CL

t10

Standard mode

Fast mode

20 + 0.1 CL

t11

Standard mode

Fast mode

20 + 0.1 CL

t11A

Standard mode

Fast mode

20 + 0.1 CL

t12

Standard mode

Fast mode

20 + 0.1 CL

tSP3

Fast mode

0

tEEPROM_PROGRAM4

15

tPOWER_UP5

tRESET

1000

300

300

300

1000

300

1000

300

300

300

50

50

50

25

Unit

kHz

kHz

µs

µs

µs

µs

ns

ns

µs

µs

µs

µs

µs

µs

µs

µs

µs

µs

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ms

µs

µs

Description

Serial clock frequency

tHIGH, SCL high time

tLOW, SCL low time

tSU;DAT, data setup time

tHD;DAT, data hold time

tSU;STA, setup time for a repeated start condition

tHD;STA, hold time (repeated) start condition

tBUF, bus free time between a stop and a start

condition

tSU;STO, setup time for stop condition

tRDA, rise time of SDA signal

tFDA, fall time of SDA signal

tRCL, rise time of SCL signal

tRCL1, rise time of SCL signal after a repeated start

condition and after an acknowledge bit.

tFCL, fall time of SCL signal

Pulse width of suppressed spike

Memory program time

Power-on EEPROM restore time

Reset EEPROM restore time

1 Maximum bus capacitance is limited to 400 pF.

2 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior

of the part.

3 Input filtering on the SCL and SDA inputs suppress noise spikes that are less than 50 ns for fast mode.

4 EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at a lower temperature and higher write cycles.

5 Maximum time after VDD is equal to 2.3 V.

Rev. 0 | Page 9 of 28

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