AD5161BRM10(Rev0) データシートの表示（PDF） - Analog Devices

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AD5161BRM10
(Rev.:Rev0)

256-Position SPI/I2C Selectable Digital Potentiometer

Analog Devices 

TEST CIRCUITS

Figure 27 to Figure 35 illustrate the test circuits that define the

test conditions used in the product specification tables.

DUT

A

V+

W

B

V+ = VDD

1LSB = V+/2N

VMS

Figure 27. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL)

NO CONNECT

DUT

A

W

B

IW

VMS

Figure 28. Test Circuit for Resistor Position Nonlinearity Error

(Rheostat Operation; R-INL, R-DNL)

VMS2

DUT

A

W

B

IW = VDD / RNOMINAL

VW

VMS1 RW = [VMS1 – VMS2]/ IW

Figure 29. Test Circuit for Wiper Resistance

VA

VDD A

V+

W

B

( ) V+= VDD 10%

PSRR (dB) = 20 LOG

∆V MS

∆V DD

PSS (%/%) = ∆VMS%

∆V DD%

VMS

Figure 30. Test Circuit for Power Supply Sensitivity (PSS, PSSR)

OFFSET

GND

A

VIN

DUT B

W

5V

OP279

OFFSET

BIAS

VOUT

Figure 31. Test Circuit for Inverting Gain

AD5161

5V

OFFSET

GND

OP279

VIN

W

A DUT B

OFFSET

BIAS

VOUT

Figure 32. Test Circuit for Noninverting Gain

A

W

VIN

DUT

OFFSET

GND

B

2.5V

+15V

AD8610

–15V

VOUT

Figure 33. Test Circuit for Gain vs. Frequency

DUT

W

B

RSW =

0.1V

ISW

CODE = 0x00

ISW

0.1V

VSS TO VDD

Figure 34. Test Circuit for Incremental ON Resistance

NC

VDD DUT

A

W

ICM

VSS GND

B

VCM

NC NC = NO CONNECT

Figure 35. Test Circuit for Common-Mode Leakage current

Rev. 0 | Page 11 of 20

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