AD7392 データシートの表示（PDF） - Analog Devices
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AD7392 Datasheet PDF : 20 Pages
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AD7392/AD7393
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
At VREF = 2.5 V, −40°C < TA < +85°C, unless otherwise noted.
Table 1. AD7392
Parameter
STATIC PERFORMANCE
Resolution1
Relative Accuracy2
Differential Nonlinearity2
Zero-Scale Error
Full-Scale Voltage Error
Full-Scale Temperature Coefficient3
REFERENCE INPUT
VREF Range
Input Resistance
Input Capacitance3
ANALOG OUTPUT
Current (Source)
Output Current (Sink)
Capacitive Load3
LOGIC INPUTS
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
Input Capacitance3
INTERFACE TIMING3, 5
Chip Select Write Width
Data Setup
Data Hold
Reset Pulse Width
AC CHARACTERISTICS
Output Slew Rate
Settling Time6
Shutdown Recovery Time
DAC Glitch
Digital Feedthrough
Feedthrough
SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current
Shutdown Supply Current
Power Dissipation
Power Supply Sensitivity
Symbol Conditions
N
INL
DNL
VZSE
VFSE
TCVFS
TA = +25°C
TA = −40°C, +85°C
TA = +25°C, monotonic
Monotonic
Data = 0x000, TA = +25°C, +85°C
Data = 0x000, TA = −40°C
TA = +25°C, +85°C, data = 0xFFF
TA = −40°C, data = 0xFFF
VREF
RREF
CREF
IOUT
Data = 0x800, ∆ VOUT = 5 LSB
IOUT
Data = 0x800, ∆ VOUT = 5 LSB
CL
No oscillation
VIL
VIH
IIL
CIL
tCS
tDS
tDH
tRS
SR
Data = 0x000 to 0xFFF to 0x000
tS
To ±0.1% of full scale
tSDR
Code 0x7FF to Code 0x800 to Code 0x7FF
VOUT/VREF VREF = 1.5 V dc + 1 V p-p, data = 0x000,
f = 100 kHz
VDD RANGE
IDD
IDD-SD
PDISS
PSS
DNL < ±1 LSB
VIL = 0 V, no load
SHDN = 0, VIL = 0 V, no load
VIL = 0 V, no load
Δ VDD = ±5%
3 V ± 10%
12
±1.8
±3
±0.9
±1
4.0
8.0
±8
±20
28
0/VDD
2.5
5
1
3
100
0.5
VDD − 0.6
10
10
45
30
20
40
0.05
70
65
15
−63
2.7/5.5
55/100
0.1/1.5
300
0.006
1 One LSB = VREF/4096 V for the 12-bit AD7392.
2 The first two codes (0x000, 0x001) are excluded from the linearity error measurement.
3 These parameters are guaranteed by design and not subject to production testing.
4 Typicals represent average readings measured at +25°C.
5 All input control signals are specified with tR = tF = 2 ns (10% to 90% of 13 V) and timed from a voltage level of 1.6 V.
6 The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground.
5 V ± 10%
12
±1.8
±3
±0.9
±1
4.0
8.0
±8
±20
28
0/VDD
2.5
5
1
3
100
0.8
VDD − 0.6
10
10
45
15
5
30
0.05
60
80
65
15
−63
2.7/5.5
55/100
0.1/1.5
500
0.006
Unit
Bits
LSB max
LSB max
LSB max
LSB max
mV max
mV max
mV max
mV max
ppm/°C typ
V min/max
MΩ typ4
pF typ
mA typ
mA typ
pF typ
V max
V min
μA max
pF max
ns min
ns min
ns min
ns min
V/μs typ
μs typ
μs typ
nV/s typ
nV/s typ
dB typ
V min/max
μA typ/max
μA typ/max
μW max
%/% max
Rev. C | Page 3 of 20
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