AD9271-50EBZ データシートの表示（PDF） - Analog Devices

部品番号

コンポーネント説明

メーカー

AD9271-50EBZ

Octal LNA/VGA/AAF/ADC and Crosspoint Switch

Analog Devices 

Preliminary Technical Data

The AD9271 requires a LVPECL-/CMOS-/LVDS-compatible

sample rate clock for full performance operation. No external

reference or driver components are required for many

applications.

The ADC automatically multiplies the sample rate clock for

the appropriate LVDS serial data rate. A data clock (DCO) for

capturing data on the output and a frame clock (FCO) trigger

for signaling a new output byte are provided.

Powering down individual channel is supported to increase battery

life for portable applications. There is also a standby mode option

that allows quick power-up for power cycling. In CW Doppler

operation, the VGA, AAF, and ADC are powered down. The

power of the TGC path scales with selectable speed grades.

The ADC contains several features designed to maximize flexibility

and minimize system cost, such as a programmable clock, data

alignment, and programmable digital test pattern generation. The

digital test patterns include built-in fixed patterns, built-in

pseudorandom pattern, and custom user-defined test patterns

entered via the serial port interface.

AD9271

Fabricated in an advanced CMOS process, the AD9271 is

available in a 14 mm × 14 mm, Pb-free, 100-lead TQFP. It is

specified over the industrial temperature range of –40°C to +85°C.

PRODUCT HIGHLIGHTS

1. Small Footprint. Eight channels are contained in a small,

space-saving package. Full TGC path, ADC, and crosspoint

switch contained within a 100-lead, 16 mm × 16 mm, TQFP.

2. Low power of 150 mW/channel at 40 MSPS.

3. Integrated Crosspoint Switch. This switch allows numerous

multichannel configuration options to enable the CW

Doppler mode.

4. Ease of Use. A data clock output (DCO) operates up to

300 MHz and supports double data rate operation (DDR).

5. User Flexibility. Serial port interface (SPI) control offers a wide

range of flexible features to meet specific system requirements.

6. Integrated Third-Order Antialiasing Filter. This filter is

placed between TGC path and ADC and is programmable

from 8 MHz to 18 MHz.

Rev. PrA | Page 3 of 58

Share Link: