AD9508(RevA) データシートの表示（PDF） - Analog Devices

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AD9508
(Rev.:RevA)

1.65 GHz Clock Fanout Buffer with Output Dividers and Delay Adjust

Analog Devices 

AD9508

Data Sheet

Parameter

OUTPUT LOGIC SKEW1

LVDS Output(s) and HSTL Output(s)

LVDS Output(s) and CMOS Output(s)

HSTL Output(s) and CMOS Output(s)

Symbol Min Typ

77

497

424

Max Unit

119 ps

700 ps

622 ps

Test Conditions/Comments

CMOS load = 10 pF and LVDS load = 100 Ω

Outputs on the same device; assumes

worst-case output combination

Outputs on the same device; assumes

worst-case output combination

Outputs on the same device; assumes

worst-case output combination

1 Output skew is the difference between any two similar delay paths while operating at the same voltage and temperature.

LOGIC INPUTS

Table 4.

Parameter

LOGIC INPUTS RESET, SYNC, IN_SEL

Input Voltage

High

Low

Input Current

Input Capacitance

Symbol Min Typ Max Unit Test Conditions/Comments

VIH

1.7

2.0

VIL

IINH, IINL

CIN

−300

2

V

V

0.7 V

0.8 V

+100 µA

pF

2.5 V supply voltage operation

3.3 V supply voltage operation

2.5 V supply voltage operation

3.3 V supply voltage operation

SERIAL PORT SPECIFICATIONS—SPI MODE

Table 5.

Parameter

CS

Input Voltage

Logic 1

Logic 0

Input Current

Logic 1

Logic 0

Input Capacitance

SCLK

Input Voltage

Logic 1

Logic 0

Input Current

Logic 1

Logic 0

Input Capacitance

SDIO

As Input

Input Voltage

Logic 1

Logic 0

Input Current

Logic 1

Logic 0

Input Capacitance

Min

VDD − 0.4

Typ Max Unit Test Conditions/Comments

SCLK has a 200 kΩ internal pull-down resistor

V

0.4

V

−4

µA

−85

µA

2

µA

VDD − 0.4

V

0.4

V

70

µA

13

µA

2

pF

VDD − 0.4

V

0.4

V

−1

µA

−1

µA

2

pF

Rev. A | Page 6 of 40

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