AD9508(RevA) データシートの表示（PDF） - Analog Devices
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AD9508 Datasheet PDF : 40 Pages
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AD9508
Data Sheet
EXTERNAL RESISTOR VALUES FOR PIN STRAPPING MODE
Table 7.
Parameter
EXTERNAL RESISTORS
Voltage Level 0
Voltage Level 1
Voltage Level 2
Voltage Level 3
Voltage Level 4
Voltage Level 5
Voltage Level 6
Voltage Level 7
Resistor Polarity
Pull down to ground
Pull down to ground
Pull down to ground
Pull down to ground
Pull up to VDD
Pull up to VDD
Pull up to VDD
Pull up to VDD
Min Typ
820
1.8
3.9
8.2
820
1.8
3.9
8.2
Max Unit Test Conditions/Comments
Using 10% tolerance resistor
Ω
kΩ
kΩ
kΩ
Ω
kΩ
kΩ
kΩ
CLOCK OUTPUT ADDITIVE PHASE NOISE
Table 8.
Parameter
Min Typ Max
CLK-TO-HSTL OR LVDS ADDITIVE PHASE NOISE
CLK = 1474.56 MHz, OUTx = 1474.56 MHz
Divide Ratio = 1
@ 10 Hz Offset
−88
@ 100 Hz Offset
−100
@ 1 kHz Offset
−109
@ 10 kHz Offset
−116
@ 100 kHz Offset
−135
@ 1 MHz Offset
−144
@ 10 MHz Offset
−148
@ 100 MHz Offset
−149
CLK-TO-HSTL OR LVDS or CMOS ADDITIVE PHASE NOISE
CLK = 625 MHz, OUTx = 125 MHz
Divide Ratio = 5
@ 10 Hz Offset
−114
@ 100 Hz Offset
−125
@ 1 kHz Offset
−133
@ 10 kHz Offset
−141
@ 100 kHz Offset
−159
@ 1 MHz Offset
−162
@ 10 MHz Offset
−163
@ 20 MHz Offset
−163
CLK-TO-HSTL OR LVDS ADDITIVE PHASE NOISE
CLK = 491.52 MHz, OUTx = 491.52 MHz
Divide Ratio = 1
@ 10 Hz Offset
−100
@ 100 Hz Offset
−111
@ 1 kHz Offset
−120
@ 10 kHz Offset
−127
@ 100 kHz Offset
−146
@ 1 MHz Offset
−153
@ 10 MHz Offset
−153
@ 20 MHz Offset
−153
Unit Test Conditions/Comments
Input slew rate > 1 V/ns
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Input slew rate > 1 V/ns
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Input slew rate > 1 V/ns
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Rev. A | Page 8 of 40
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