AD9508BCPZ データシートの表示（PDF） - Analog Devices
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AD9508BCPZ Datasheet PDF : 40 Pages
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AD9508
Parameter
As Output
Output Voltage
Logic 1
Logic 0
SDO
Output Voltage
Logic 1
Logic 0
TIMING
SCLK
Clock Rate, 1/tCLK
Pulse Width High, tHIGH
Pulse Width Low, tLOW
SDIO to SCLK Setup, tDS
SCLK to SDIO Hold, tDH
SCLK to Valid SDIO and SDO, tDV
CS to SCLK Setup (tS)
CS to SCLK Hold (tC)
CS to Minimum Pulse Width High
Min
Typ Max Unit Test Conditions/Comments
VDD − 0.4
V
0.4
V
1 mA load current
1 mA load current
VDD − 0.4
V
0.4
V
1 mA load current
1 mA load current
30
MHz
4.6
ns
3.5
ns
2.9
ns
0
ns
15
ns
3.4
ns
0
ns
3.4
ns
Data Sheet
SERIAL PORT SPECIFICATIONS—I2C MODE
Table 6.
Parameter
SDA, SCL (AS INPUT)
Input Voltage
Logic 1
Logic 0
Input Current
Hysteresis of Schmitt Trigger Inputs
SDA (AS OUTPUT)
Output Logic 0 Voltage
Output Fall Time from VIH (MIN) to VIL (MAX)
TIMING
SCL Clock Rate
Bus-Free Time Between a Stop and Start
Condition, tBUF
Repeated Start Condition Setup Time, tSU; STA
Repeated Hold Time Start Condition, tHD; STA
Min
Typ Max
VDD − 0.4
0.4
−40
0
150
0.4
250
400
1.3
0.6
0.6
Stop Condition Setup Time, tSU; STO
0.6
Low Period of the SCL Clock, tLOW
1.3
High Period of the SCL Clock, tHIGH
0.6
Data Setup Time, tSU; DAT
100
Data Hold Time, tHD; DAT
0
0.9
Unit Test Conditions/Comments
V
V
µA For VIN = 10% to 90% DVDD3
mV
V
IO = 3 mA
ns 10 pF ≤ Cb ≤ 400 pF
kHz
µs
µs
µs After this period, the first clock pulse is
generated
µs
µs
µs
ns
µs
Rev. G | Page 8 of 40
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