AD9516-1(Rev0) データシートの表示（PDF） - Analog Devices
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AD9516-1 Datasheet PDF : 84 Pages
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AD9516-1
DELAY BLOCK ADDITIVE TIME JITTER
Table 13.
Parameter
DELAY BLOCK ADDITIVE TIME JITTER1
100 MHz Output
Delay (1600 μA, 1C) Fine Adj. 000000
Delay (1600 μA, 1C) Fine Adj. 101111
Delay (800 μA, 1C) Fine Adj. 000000
Delay (800 μA, 1C) Fine Adj. 101111
Delay (800 μA, 4C) Fine Adj. 000000
Delay (800 μA, 4C) Fine Adj. 101111
Delay (400 μA, 4C) Fine Adj. 000000
Delay (400 μA, 4C) Fine Adj. 101111
Delay (200 μA, 1C) Fine Adj. 000000
Delay (200 μA, 1C) Fine Adj. 101111
Delay (200 μA, 4C) Fine Adj. 000000
Delay (200 μA, 4C) Fine Adj. 101111
Min Typ Max Unit
0.54
ps rms
0.60
ps rms
0.65
ps rms
0.85
ps rms
0.79
ps rms
1.2
ps rms
1.2
ps rms
2.0
ps rms
1.3
ps rms
2.5
ps rms
1.9
ps rms
3.8
ps rms
Test Conditions/Comments
Incremental additive jitter
1 This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter
should be added to this value using the root sum of squares (RSS) method.
SERIAL CONTROL PORT
Table 14.
Parameter
CS (INPUT)
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
SCLK (INPUT)
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
SDIO (WHEN INPUT)
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
SDIO, SDO (OUTPUTS)
Output Logic 1 Voltage
Output Logic 0 Voltage
Min Typ Max Unit Test Conditions/Comments
CS has an internal 30 kΩ pull-up resistor
2.0
V
0.8 V
3
μA
110
μA
2
pF
SCLK has an internal 30 kΩ pull-down resistor
2.0
V
0.8 V
110
μA
1
μA
2
pF
2.0
V
0.8 V
10
nA
20
nA
2
pF
2.7
V
0.4 V
Rev. 0 | Page 12 of 84
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