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AD96685(RevD) データシートの表示(PDF) - Analog Devices

部品番号
コンポーネント説明
メーカー
AD96685
(Rev.:RevD)
ADI
Analog Devices 
AD96685 Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
AD96685/AD96687–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (Positive Supply Voltage = 5.0 V; Negative Supply Voltage = –5.2 V, unless otherwise noted.)
Parameter
Temp
Test
Level
Industrial Temperature Range –25؇C to +85؇C
AD96685BR
Min Typ Max
AD96687BQ/BP/BR
Min Typ Max
INPUT CHARACTERISTICS
Input Offset Voltage
25°C
I
Full
VI
Input Offset Drift
Full
V
Input Bias Current
25°C
I
Full
VI
Input Offset Current
25°C
I
Full
VI
Input Resistance
25°C
V
Input Capacitance
Input Voltage Ranges2
25°C
V
Full
VI
Common-Mode Rejection Ratio
Full
VI
1
2
3
20
7
10
13
0.1 1.0
1.2
200
2
–2.5
+5.0
80 90
1
20
7
0.1
200
2
–2.5
80
90
2
3
10
13
1.0
1.2
+5.0
ENABLE INPUT
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
DIGITAL OUTPUTS3
Logic “1” Voltage
Logic “0” Voltage
Full
VI
–1.1
–1.1
Full
VI
–1.5
–1.5
Full
VI
40
40
Full
VI
5
5
Full
VI
–1.1
–1.1
Full
VI
–1.5
–1.5
SWITCHING PERFORMANCES
Propagation Delays4
Input to Output HIGH
25°C
IV
Input to Output LOW
25°C
IV
Latch Enable to Output HIGH
25°C
IV
Latch Enable to Output LOW
25°C
IV
Dispersions5
25°C
V
Latch Enable
Minimum Pulsewidth
25°C
IV
Minimum Setup Time
25°C
IV
Minimum Hold Time
25°C
IV
POWER SUPPLY6
Positive Supply Current (+5.0 V)
Full
VI
Negative Supply Current (–5.2 V)
Full
VI
Power Supply Rejection Ratio7
Full
VI
2.5 3.5
2.5 3.5
2.5 3.5
2.5 3.5
50
2.0 3.0
0.5 1.0
0.5 1.0
8
9
15 18
60 70
2.5 3.5
2.5 3.5
2.5 3.5
2.5 3.5
50
2.0 3.0
0.5 1.0
0.5 1.0
15
18
31
36
60
70
NOTES
1RS = 100 .
2Input Voltage Range can be extended to –3.3 V if –VS = –6.0 V.
3Outputs terminated through 50 to –2.0 V.
4Propagation delays measured with 100 mV pulse (10 mV overdrive) to 50% transition point of the output.
5Change in propagation delay from 100 mV to 1 V input overdrive.
6Supply voltages should remain stable within ± 5% for normal operation.
7Measured at ± 5% of +VS and –VS.
Specifications subject to change without notice.
Unit
mV
mV
µV/°C
µA
µA
µA
µA
k
pF
V
dB
V
V
µA
µA
V
V
ns
ns
ns
ns
ps
ns
ns
ns
mA
mA
dB
COMPARE
LATCH
ENABLE
LATCH
DIFFERENTIAL
INPUT
VOLTAGE
VIN
Q
tS
tH
VDD
tPD
Q
tPW(E)
tPD(E)
50%
VOS
50%
50%
tS
Minimum Setup Time
tH
Minimum Hold Time
tPD Input to Output Delay
tPD(E) LATCH ENABLE to Output Delay
tPW(E) Minimum LATCH ENABLE Pulsewidth
VOS Input Offset Voltage
VOD Overdrive Voltage
Figure 1. System Timing Diagram
–2–
REV. D

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