AD9748 データシートの表示（PDF） - Analog Devices
部品番号
コンポーネント説明
メーカー
AD9748 Datasheet PDF : 20 Pages
| |||
AD9748
The positive output compliance range is slightly dependent on the
full-scale output current, IOUTFS. It degrades slightly from its nomi-
nal 1.2 V for an IOUTFS = 20 mA to 1.0 V for an IOUTFS = 2 mA.
The optimum distortion performance for a single-ended or
differential output is achieved when the maximum full-scale signal
at IOUTA and IOUTB does not exceed 0.5 V.
DIGITAL INPUTS
The AD9748 digital section consists of 8 input bit channels and
a clock input. The 8-bit parallel data inputs follow standard posi-
tive binary coding, where DB7 is the most significant bit (MSB)
and DB0 is the least significant bit (LSB). IOUTA produces a full-
scale output current when all data bits are at Logic 1. IOUTB
produces a complementary output with the full-scale current
split between the two outputs as a function of the input code.
DVDD
output. Optimal performance will be achieved if the CLOCK
input has a sharp rising edge, since the DAC latches are positive
edge triggered.
In the differential input mode, the clock input functions as a
high impedance differential pair. The common-mode level of
the CLK+ and CLK– inputs can vary from 0.75 V to 2.25 V,
and the differential voltage can be as low as 0.5 V p-p. This mode
can be used to drive the clock with a differential sine wave, since
the high gain-bandwidth of the differential inputs will convert
the sine wave into a single-ended square wave internally.
The final clock mode allows for a reduced external component
count when the DAC clock is distributed on the board using
PECL logic. The internal termination configuration is shown in
Figure 7. These termination resistors are untrimmed and the
absolute resistance can vary up to ± 20%. However, matching
between the resistors should be generally better than ± 1%.
DIGITAL
INPUT
Figure 6. Equivalent Digital Input
The digital interface is implemented using an edge-triggered
master/slave latch. The DAC output updates on the rising edge
of the clock and is designed to support a clock rate as high as
165 MSPS. The clock can be operated at any duty cycle that
meets the specified latch pulsewidth. The setup and hold times
can also be varied within the clock cycle as long as the specified
minimum times are met, although the location of these transition
edges may affect digital feedthrough and distortion performance.
Best performance is typically achieved when the input data
transitions on the falling edge of a 50% duty cycle clock.
CLOCK INPUT
A configurable clock input allows for one single-ended and two
differential modes. The mode selection is controlled by the
CMODE input, as summarized in Table I. Connecting CMODE
to CLKCOM selects the single-ended clock input. In this mode,
the CLK+ input is driven with rail-to-rail swings and the CLK–
input is left floating. If CMODE is connected to CLKVDD, the
differential receiver mode is selected. In this mode both inputs are
high impedance. The final mode is selected by floating CMODE.
This mode is also differential, but internal terminations for
positive emitter-coupled logic (PECL) are activated. There is no
significant performance difference between any of the three clock
input modes.
Table I. Clock Mode Selection
CMODE Pin
CLKCOM
CLKVDD
Float
Clock Input Mode
Single-Ended
Differential
PECL
In the single-ended clock input mode, the CLK+ pin must be
driven to rail-to-rail CMOS levels. The quality of the DAC output
is directly related to the clock quality, and jitter is a key concern.
Any noise or jitter in the clock will translate directly into the DAC
CLK+
CLK–
50⍀
AD9748
CLOCK
RECEIVER
50⍀
TO DAC CORE
VTT = 1.3V NOM
Figure 7. Clock Termination in PECL Mode
DAC TIMING
Input Clock and Data Timing Relationship
Dynamic performance in a DAC is dependent on the relation-
ship between the position of the clock edges and the time at
which the input data changes. The AD9748 is rising edge trig-
gered, and so exhibits dynamic performance sensitivity when the
data transition is close to this edge. In general, the goal when
applying the AD9748 is to make the data transition close to the
falling clock edge. This becomes more important as the sample
rate increases. Figure 8 shows the relationship of SFDR to clock
placement with different sample rates. Note that at the lower
sample rates, more tolerance is allowed in clock placement, while
at higher rates, more care must be taken.
80
75
20MHz SFDR
70
65
60
55
50MHz SFDR
50
45
40
35
30
0
2
4
6
8
10 12
CLOCK PLACEMENT – ns
Figure 8. SFDR vs. Clock Placement @ fOUT = 20 MHz
and 50 MHz (fCLOCK = 165 MSPS)
–10–
REV. 0
Share Link: 