AD9838 データシートの表示（PDF） - Analog Devices

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AD9838

Mixed-Signal Front-End (MxFE) Processor for Broadband Communications

Analog Devices 

AD9838

DATA WRITE

(SEE FIGURE 26)

SELECT DATA

SOURCES

(SEE FIGURE 27)

WAIT 8/9 MCLK

CYCLES

(SEE TIMING DIAGRAM

FIGURE 3)

INITIALIZATION

(SEE FIGURE 25)

DAC OUTPUT

VOUT = VREFOUT × 18 × RLOAD/RSET × (1 + (SIN(2π(FREQREG × fMCLK × t/228 + PHASEREG/212))))

CHANGE PHASE?

YES

CHANGE PSEL/

PSELECT?

YES

NO

NO

YES

CHANGE FSEL/

FSELECT?

YES

CHANGE FREQUENCY?

CHANGE PHASE

REGISTER?

NO

NO

YES

YES CHANGE FREQUENCY

REGISTER?

YES

CHANGE DAC OUTPUT

FROM SIN TO TRIANGLE?

NO

CONTROL

REGISTER

WRITE

(SEE TABLE 7)

YES

CHANGE OUTPUT AT

SIGN BIT OUT PIN?

NO

Figure 24. Flowchart for AD9838 Initialization and Operation

INITIALIZATION

USING CONTROL

BIT

APPLY RESET

USING PIN

(CONTROL REGISTER WRITE)

RESET = 1

PIN/SW = 0

(CONTROL REGISTER WRITE)

PIN/SW = 1

SET RESET PIN = 1

WRITE TO FREQUENCY AND PHASE REGISTERS

FREQ0 REG = fOUT0/fMCLK × 228

FREQ1 REG = fOUT1/fMCLK × 228

PHASE0 AND PHASE1 REG = (PHASESHIFT × 212)/2π

(SEE FIGURE 26)

USING CONTROL

BITS

SET RESET = 0

SELECT FREQUENCY REGISTERS

SELECT PHASE REGISTERS

USING PINS

(CONTROL REGISTER WRITE)

RESET BIT = 0

FSEL = SELECTED FREQUENCY REGISTER

PSEL = SELECTED PHASE REGISTER

PIN/SW = 0

(APPLY SIGNALS AT PINS)

RESET PIN = 0

FSELECT = SELECTED FREQUENCY REGISTER

PSELECT = SELECTED PHASE REGISTER

PIN/SW = 1

Figure 25. Flowchart for Initialization

Rev. A | Page 22 of 32

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