AD9858(RevA) データシートの表示（PDF） - Analog Devices

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AD9858
(Rev.:RevA)

1 GSPS Direct Digital Synthesizer

Analog Devices 

Pin No.

71

72

78

79

81, 82

83, 84

91

92

97, 98

99

100

AD9858

Mnemonic I/O Description

DIV

I Phase Frequency Detector Feedback Input.

DIV

I Phase Frequency Detector Feedback Complementary Input. Note that when the DIV port is

operated in single-ended mode, DIV should be decoupled to AVDD with a 0.1 µF capacitor.

DACBP

DAC Baseline Decoupling Pin, Typically Bypassed to Pin 77 with a 0.1 µF Capacitor.

DACISET I A Resistor Connected from DACISET to AGND Establishes the Reference Current for the DAC.

IOUT

O DAC Output.

IOUT

O DAC Complementary Output.

SPSELECT I

I/O Port Serial/Parallel Programming Mode Select Pin. Logic 0: serial programming mode.

Logic 1: parallel programming mode.

RESET

I Active High Hardware Reset Pin. Assertion of the RESET pin forces the AD9858 to its default

operating conditions.

PS0, PS1 I Used to Select One of the Four Internal Profiles. These pins are synchronous to the

SYNCLK output.

FUD

I Frequency Update. The rising edge transfers the contents of the internal buffer registers to the

memory registers. This pin is synchronous to the SYNCLK output.

SYNCLK

O Clock Output Pin that Serves as a Synchronizer for External Hardware. SYNCLK runs at REFCLK/8.

Rev. A | Page 9 of 32

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