NXP Semiconductors
ADC1003S030/040/050
Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage
regulator
VCCD
CLK
DGND
1.5 V
Fig 13. CLK input
12. Application information
12.1 Application diagram
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CLK
1
TC
2
VCCA
3
(3) 100 nF AGND
4
VCCD1
28
DGND1 (3) 100 nF
27
IR
26
D9
25
4.7 nF
AGND
1 nF
1 nF
AGND
AGND
DEC
5
24 D8
RB(1)
6
D7
23
RM(1)
D6
7
22
VI ADC1003S050 D5
8
21
RT(1)
9
20 D4
100 nF
OE
10
D3
19
AGND (3)
(3)
VCCD2
11
100 nF DGND2
12
VCCO
13
100 nF OGND
14
D2
18
D1
17
16 D0
n.c.(2)
15
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The analog and digital supplies should be separated and well decoupled.
A user manual is available that describes the demonstration board that uses the ADC1003S030/040/050 family in an
application environment.
(1) RB, RM and RT are decoupled to AGND.
(2) Pin 15 may be connected to DGND in order to prevent noise influence.
(3) Decoupling capacitor for supplies: must be placed close to the device.
Fig 14. Application diagram
ADC1003S030_040_050_2
Product data sheet
Rev. 02 — 7 August 2008
© NXP B.V. 2008. All rights reserved.
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