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EVAL-ADCMP572BCPZ(RevB) データシートの表示(PDF) - Analog Devices

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EVAL-ADCMP572BCPZ
(Rev.:RevB)
ADI
Analog Devices 
EVAL-ADCMP572BCPZ Datasheet PDF : 14 Pages
First Prev 11 12 13 14
Data Sheet
ADCMP572/ADCMP573
TIMING INFORMATION
Figure 29 illustrates the ADCMP572/ADCMP573 compare and latch timing relationships. Table 4 provides definitions of the terms
shown in the figure.
LATCH ENABLE
50%
LATCH ENABLE
tS
tPL
tH
DIFFERENTIAL
VIN
INPUT VOLTAGE
VOD
VN ± VOS
Q OUTPUT
Q OUTPUT
tPDL
tPLOH
50%
tPDH
tF
50%
tPLOL
tR
Figure 29. System Timing Diagram
Table 4. Timing Descriptions
Symbol Timing
tPDH
Input to output high delay
tPDL
Input to output low delay
tPLOH
Latch enable to output high delay
tPLOL
Latch enable to output low delay
tH
Minimum hold time
tPL
Minimum latch enable pulse width
tS
Minimum setup time
tR
Output rise time
tF
Output fall time
VOD
Voltage overdrive
Description
Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output low-to-high transition.
Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output high-to-low transition.
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output low-to-high transition.
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output high-to-low transition.
Minimum time after the negative transition of the latch enable signal that the input
signal must remain unchanged to be acquired and held at the outputs.
Minimum time that the latch enable signal must be high to acquire an input signal
change.
Minimum time before the negative transition of the latch enable signal that an input
signal change must be present to be acquired and held at the outputs.
Amount of time required to transition from a low to a high output as measured at the
20% and 80% points.
Amount of time required to transition from a high to a low output as measured at the
20% and 80% points.
Difference between the input voltages VA and VB.
Rev. B | Page 13 of 14

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