ADL5565-EVALZ(Rev0) データシートの表示（PDF） - Analog Devices
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ADL5565-EVALZ Datasheet PDF : 28 Pages
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ADL5565
INPUT AND OUTPUT INTERFACING
The ADL5565 can be configured as a differential input to
differential output driver, as shown in Figure 32. The resistors,
R1 and R2, combined with the ETC1-1-13 balun transformer,
provide a 50 Ω input match for the three input impedances that
change with the variable gain strapping. The input and output
0.1 μF capacitors isolate the VCC/2 bias from the source and
balanced load. The load should equal 200 Ω to provide the
expected ac performance (see the Specifications section and the
Typical Performance Characteristics section).
3V TO 5V
50Ω
AC
ETC1-1-13 0.1µF A
R2
0.1µF
B
R1
VIP2
VIP1
VIN1
VIN2
0.1µF
RL
2
RL
0.1µF 2
NOTES
1. FOR 6dB GAIN (AV = 2), CONNECT INPUT A TO VIP1 AND INPUT B TO VIN1.
2. FOR 12dB GAIN (AV = 4), CONNECT INPUT A TO VIP2 AND INPUT B TO VIN2.
3. FOR 15.5dB GAIN (AV = 6), CONNECT INPUT A TO BOTH VIP1 AND VIP2
AND INPUT B TO BOTH VIN1 AND VIN2.
Figure 32. Differential Input to Differential Output Configuration
Table 5. Differential Termination Values for Figure 32
Gain (dB)
R1 (Ω)
R2 (Ω)
6
29
29
12
33
33
15.5
40.2
40.2
The differential gain of the ADL5565 is dependent on the source
impedance and load, as shown in Figure 33.
0.1µF
200Ω
1/2 RS
AC
1/2 RS
0.1µF
VIP2 50Ω
VIP1 100Ω
VIN1 100Ω
VIN2 50Ω
200Ω
5Ω
RL
5Ω
Figure 33. Differential Input Loading Circuit
The differential gain can be determined using the following
formula. The values of RG for each gain configuration are shown
in Table 6.
AV
=
200 × RL
RG 10 + RL
(1)
In Equation 1, RG is the gain setting resistor (see Figure 1).
Table 6. Values of RG for Differential Gain
Gain (dB)
RG (Ω)
6
100
12
50
15.5
33.5
Single-Ended Input to Differential Output
The ADL5565 can also be configured in a single-ended input
to differential output driver, as shown in Figure 34. In this
configuration, the gain of the part is reduced due to the application
of the signal to only one side of the amplifier. The strappable
gain values are listed in Table 7 with the required terminations
to match to a 50 Ω source using R1 and R2. The input and output
0.1 μF capacitors isolate the VCC/2 bias from the source and the
balanced load. The performance for this configuration is shown
in Figure 16 and Figure 21.
3V TO 5V
50Ω
AC
0.1µF A
VIP2
VIP1
R2
VIN1
B
VIN2
+
0.1µF
R1
0.1µF
RL
2
RL
0.1µF 2
NOTES
1. FOR 5.3dB GAIN (AV = 1.84), CONNECT INPUT A TO VIP1
AND INPUT B TO VIN1.
2. FOR 10.3dB GAIN (AV = 3.3), CONNECT INPUT A TO VIP2
AND INPUT B TO VIN2.
3. FOR 13dB GAIN (AV = 4.5), CONNECT INPUT A TO BOTH
VIP1 AND VIP2 AND INPUT B TO BOTH VIN1 AND VIN2.
Figure 34. Single-Ended Input to Differential Output Configuration
Table 7. Single-Ended Termination Values for Figure 34
Gain (dB)
R1 (Ω)
R2 (Ω)
5.3
30
73
10.3
30
104
13
30
154
The single-ended gain configuration of the ADL5565 is dependent
on the source impedance and load, as shown in Figure 35.
RS
AC
0.1µF
R2
VIP2 50Ω
VIP1 100Ω
VIN1 100Ω
VIN2 50Ω
+
0.1µF
R1
200Ω
200Ω
5Ω
0.1µF
RL
2
5Ω
0.1µF
RL
2
Figure 35. Single-Ended Input Loading Circuit
Rev. 0 | Page 18 of 28
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