ADN2816(RevPrA) データシートの表示（PDF） - Analog Devices
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ADN2816 Datasheet PDF : 27 Pages
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Preliminary Technical Data
period, the user should issue one start condition, one stop
condition, or a single stop condition followed by a single start
condition. If an invalid subaddress is issued by the user, the
ADN2816 does not issue an acknowledge and returns to the idle
condition. If the user exceeds the highest subaddress while
reading back in autoincrement mode, then the highest subad-
dress register contents continue to be output until the master
device issues a no-acknowledge. This indicates the end of a
read. In a no-acknowledge condition, the SDATA line is not
pulled low on the ninth pulse. See Figure 6 and Figure 7 for
sample read and write data transfers and Figure 8 for a more
detailed timing diagram.
REFERENCE CLOCK (OPTIONAL)
A reference clock is not required to perform clock and data
recovery with the ADN2816. However, support for an optional
reference clock is provided. The reference clock can be driven
differentially or single-ended. If the reference clock is not being
used, then REFCLKP should be tied to VCC, and REFCLKN
can be left floating or tied to VEE (the inputs are internally
terminated to VCC/2). See Figure 15 through Figure 17 for
sample configurations.
The REFCLK input buffer accepts any differential signal with a
peak-to-peak differential amplitude of greater than 100 mV (for
example, LVPECL or LVDS) or a standard single-ended low
voltage TTL input, providing maximum system flexibility.
Phase noise and duty cycle of the reference clock are not critical
and 100 ppm accuracy is sufficient.
ADN2816
REFCLKP
10
BUFFER
11
REFCLKN
100kΩ 100kΩ
VCC/2
Figure 15. Differential REFCLK Configuration
VCC
REFCLKP
CLK
OSC OUT
REFCLKN
ADN2816
BUFFER
100kΩ 100kΩ
VCC/2
Figure 16. Single-Ended REFCLK Configuration
ADN2816
VCC
ADN2816
10
REFCLKP
BUFFER
11
NC
REFCLKN
100kΩ 100kΩ
VCC/2
Figure 17. No REFCLK Configuration
The two uses of the reference clock are mutually exclusive. The
reference clock can be used either as an acquisition aid for the
ADN2816 to lock onto data, or to measure the frequency of the
incoming data to within 0.01%. (There is the capability to
measure the data rate to approximately ±10% without the use of
a reference clock.) The modes are mutually exclusive, because,
in the first use, the user knows exactly what the data rate is and
wants to force the part to lock onto only that data rate; in the
second use, the user does not know what the data rate is and
wants to measure it.
Lock to reference mode is enabled by writing a 1 to I2C Register
Bit CTRLA[0]. Fine data rate readback mode is enabled by
writing a 1 to I2C Register Bit CTRLA[1]. Writing a 1 to both of
these bits at the same time causes an indeterminate state and is
not supported.
Using the Reference Clock to Lock onto Data
In this mode, the ADN2816 locks onto a frequency derived
from the reference clock according to the following equation:
Data Rate/2CTRLA[5:2] = REFCLK/2CTRLA[7:6]
The user must know exactly what the data rate is, and provide a
reference clock that is a function of this rate. The ADN2816 can
still be used as a continuous rate device in this configuration,
provided that the user has the ability to provide a reference
clock that has a variable frequency (see Application Note
AN-632).
The reference clock can be anywhere between 12.3 MHz and
200 MHz. By default, the ADN2816 expects a reference clock of
between 12.3 MHz and 25 MHz. If it is between 25 MHz and
50 MHz, 50 MHz and 100 MHz, or 100 MHz and 200 MHz, the
user needs to configure the ADN2816 to use the correct
reference frequency range by setting two bits of the CTRLA
register, CTRLA[7:6].
Table 11. CTRLA Settings
CTRLA[7:6] Range (MHz)
00
12.3 to 25
01
25 to 50
10
50 to 100
11
100 to 200
CTRLA[5:2]
0000
0001
n
1000
Ratio
1
2
2n
256
Rev. PrA | Page 17 of 27
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