ADP1707ARDZ-1.8-R7(RevA) データシートの表示（PDF） - Analog Devices

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ADP1707ARDZ-1.8-R7
(Rev.:RevA)

1 A, Low Dropout, CMOS Linear Regulator

Analog Devices 

ADP1706/ADP1707/ADP1708

Data Sheet

OUTLINE DIMENSIONS

5.00

4.90

4.80

3.098

0.356

8

5

6.20

4.00 6.00

3.90 5.80

3.80

0.457

1

4

1.27 BSC

1.75

1.35

TOP VIEW

3.81 REF

1.65

1.25

BOTTOM VIEW

0.50 45°

0.25

SEATING

PLANE

0.10 MAX

0.51

0.31

0.05 NOM

8°

COPLANARITY

0°

0.10

1.04 REF

2.41

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

0.25

0.17

1.27

0.40

COMPLIANT TO JEDEC STANDARDS MS-012-A A

Figure 43. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP]

Narrow Body

(RD-8-2)

Dimensions shown in millimeters

PIN 1 INDEX

AREA

0.80

0.75

0.70

SEATING

PLANE

3.10

3.00 SQ

2.90

1.84

1.74

1.64

5

0.50 BSC

8

TOP VIEW

0.30

0.25

0.20

0.50

0.40

0.30

EXPOSED

PAD

1.55

1.45

1.35

4

1

BOTTOM VIEW

PIN 1

INDICATOR

(R 0.15)

0.05 MAX

0.02 NOM

COPLANARITY

0.08

0.203 REF

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

COMPLIANT TO JEDEC STANDARDS MO-229-WEED

Figure 44. 8-Lead Frame Chip Scale Package [LFCSP]

3 mm × 3 mm Body and 0.75 mm Package Height

(CP-8-13)

Dimensions shown in millimeters

Rev. A | Page 18 of 20

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