ADP5024ACPZ-R2 データシートの表示（PDF） - Analog Devices

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ADP5024ACPZ-R2

Dual 3 MHz, 1200 mA Buck Regulators with One 300 mA LDO

Analog Devices 

ADP5024

PCB LAYOUT GUIDELINES

Poor layout can affect ADP5024 performance, causing electro-

magnetic interference (EMI) and electromagnetic compatibility

(EMC) problems, ground bounce, and voltage losses. Poor

layout can also affect regulation and stability. A good layout is

implemented using the following guidelines. Also, refer to User

Guide UG-271.

• Place the inductor, input capacitor, and output capacitor

close to the IC using short tracks. These components carry

high switching frequencies, and large tracks act as antennas.

• Route the output voltage path away from the inductor and

SW node to minimize noise and magnetic interference.

Data Sheet

• Maximize the size of ground metal on the component side

to help with thermal dissipation.

• Use a ground plane with several vias connected to the

component side ground to further reduce noise

interference on sensitive circuit nodes.

• Connect VIN1, VIN2, and AVIN together close to the IC

using short tracks.

Rev. E | Page 26 of 28

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