ADT7461AARMZ-2 データシートの表示（PDF） - Analog Devices
部品番号
コンポーネント説明
メーカー
ADT7461AARMZ-2 Datasheet PDF : 24 Pages
| |||
ADT7461A
SPECIFICATIONS
TA = −40°C to +125°C, VDD = 3 V to 3.6 V, unless otherwise noted.
Table 2.
Parameter
POWER SUPPLY
Supply Voltage, VDD
Average Operating Supply Current, IDD
Undervoltage Lockout Threshold
Power-On-Reset Threshold
TEMPERATURE-TO-DIGITAL CONVERTER
Local Sensor Accuracy
Resolution
Remote Diode Sensor Accuracy
Resolution
Remote Sensor Source Current
Conversion Time
Min Typ Max Unit
3.0 3.30 3.6 V
240 350 μA
5
30 μA
2.55
V
1
2.5 V
±1 °C
±1.5 °C
±2.5 °C
1
°C
±1 °C
±1.5 °C
±2.5 °C
0.25
°C
220
μA
82
μA
13.5
μA
40 52 ms
6
8
ms
Maximum Series Resistance Cancelled
1. 5
kΩ
OPEN-DRAIN DIGITAL OUTPUTS
(THERM, ALERT/THERM2)
Output Low Voltage, VOL
0.4 V
High Level Output Leakage Current, IOH
0.1 1
μA
SMBus INTERFACE3, 4
Logic Input High Voltage, VIH
2.1
V
SCLK, SDATA
Logic Input Low Voltage, VIL
0.8 V
SCLK, SDATA
Hysteresis
500
mV
SDA Output Low Voltage, VOL
0.4 V
Logic Input Current, IIH, IIL
−1
+1 μA
SMBus Input Capacitance, SCLK, SDATA
5
pF
SMBus Clock Frequency
400 kHz
SMBus Timeout5
25 64 ms
SCLK Falling Edge to SDATA Valid Time
1
μs
Test Conditions
0.0625 conversions/sec rate1
Standby mode
VDD input, disables ADC, rising edge
0°C ≤ TA ≤ +70°C
0°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +100°C
0°C ≤ TA ≤ +70°C, −55°C ≤ TD2 ≤ +150°C
0°C ≤ TA ≤ +85°C, −55°C ≤ TD2 ≤ +150°C
−40°C ≤ TA ≤ +100°C, −55°C ≤ TD2 ≤ +150°C
High level3
Middle level3
Low level3
From stop bit to conversion complete, one-shot mode with
averaging switched on
One-shot mode with averaging off
(that is, conversion rate = 16-, 32-, or 64-conversions per
second)
Resistance split evenly on both the D+ and D– inputs
IOUT = −6.0 mA
VOUT = VDD
3 V ≤ VDD ≤ 3.6 V
3 V ≤ VDD ≤ 3.6 V
IOUT = −6.0 mA
User programmable
Master clocking in data
1 See Table 10 for information on other conversion rates.
2 Guaranteed by characterization, but not production tested.
3 Guaranteed by design, but not production tested.
4 See SMBus Timing Specifications section for more information.
5 Disabled by default. Detailed procedures to enable it are in the Serial Bus Interface section of this data sheet.
Rev. A | Page 4 of 24
Share Link: 