ADT7461ARM-REEL データシートの表示（PDF） - ON Semiconductor

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ADT7461ARM-REEL

±1°C Temperature Monitor with Series Resistance Cancellation

ON Semiconductor 

ADT7461

high period, since a low-to-high transition when

the clock is high may be interpreted as a stop

signal. The number of data bytes that can be

transmitted over the serial bus in a single read or

write operation is limited only by what the master

and slave devices can handle.

3. When all data bytes have been read or written,

stop conditions are established. In write mode, the

master pulls the data line high during the tenth

clock pulse to assert a stop condition. In read

mode, the master device overrides the

acknowledge bit by pulling the data line high

during the low period before the ninth clock pulse.

This is known as a no acknowledge. The master

then takes the data line low during the low period

before the tenth clock pulse, then high during the

tenth clock pulse to assert a stop condition.

Any number of bytes of data may be transferred over the

serial bus in one operation, but it is not possible to mix read

1

SCLK

and write in one operation because the type of operation is

determined at the beginning and cannot subsequently be

changed without starting a new operation. With the

ADT7461, write operations contain either one or two bytes,

while read operations contain one byte.

To write data to one of the device data registers or to read

data from it, the address pointer register must be set so that

the correct data register is addressed. The first byte of a write

operation always contains a valid address that is stored in the

address pointer register. If data is to be written to the device,

the write operation contains a second data byte that is written

to the register selected by the address pointer register.

This is illustrated in Figure 16. The device address is sent

over the bus followed by R/W set to 0. This is followed by two

data bytes. The first data byte is the address of the internal data

register to be written to, which is stored in the address pointer

register. The second data byte is the data to be written to the

internal data register. The examples shown in Figure 16 to

Figure 18 use the ADT7461 SMBus Address 0x4C.

9

1

9

SDATA

A6

START BY

MASTER

A5 A4 A3 A2 A1 A0

FRAME 1

SERIAL BUS ADDRESS BYTE

R/W

D7

ACK. BY

ADT7461

D6 D5 D4 D3 D2 D1 D0

ACK. BY

ADT7461

FRAME 2

ADDRESS POINTER REGISTER BYTE

1

9

SCLK (CONTINUED)

SDATA (CONTINUED)

D7 D6 D5 D4 D3 D2 D1 D0

FRAME 3

DATA BYTE

ACK. BY STOP BY

ADT7461 MASTER

Figure 16. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register

1

9

1

9

SCLK

SDATA

A6

START BY

MASTER

A5 A4 A3 A2 A1 A0 R/W

D7

ACK. BY

ADT7461

FRAME 1

SERIAL BUS ADDRESS BYTE

D6 D5 D4 D3 D2 D1 D0

ACK. BY

ADT7461

FRAME 2

ADDRESS POINTER REGISTER BYTE

STOP BY

MASTER

Figure 17. Writing to the Address Pointer Register Only

1

9

1

9

SCLK

SDATA

A6

START BY

MASTER

A5 A4 A3 A2 A1 A0 R/W

D7 D6

FRAME 1

SERIAL BUS ADDRESS BYTE

ACK. BY

ADT7461

D5 D4 D3 D2 D1

FRAME 2

DATA BYTE FROM ADT7461

D0

NACK. BY STOP BY

MASTER MASTER

Figure 18. Reading from a Previously Selected Register

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