ADUM1250SRZ データシートの表示（PDF） - Analog Devices
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ADUM1250SRZ Datasheet PDF : 16 Pages
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ADuM1250/ADuM1251
Data Sheet
AC Specifications1
All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical
specifications are at TA = 25°C, VDD1 = 3.3 V or 5 V, and VDD2 = 3.3 V or 5 V, unless otherwise noted. Refer to Figure 5.
Table 2.
Parameter
MAXIMUM FREQUENCY
OUTPUT FALL TIME
5 V Operation
Symbol
Min Typ
1000
Side 1 Output (0.9 VDD1 to 0.9 V)
tf1
Side 2 Output (0.9 VDD2 to 0.1 VDD2)
tf2
3 V Operation
13
26
32
52
Side 1 Output (0.9 VDD1 to 0.9 V)
tf1
Side 2 Output (0.9 VDD2 to 0.1 VDD2)
tf2
PROPAGATION DELAY
5 V Operation
13
32
32
61
Side 1 to Side 2, Rising Edge2
tPLH12
95
Side 1 to Side 2, Falling Edge3
tPHL12
162
Side 2 to Side 1, Rising Edge4
tPLH21
31
Side 2 to Side 1, Falling Edge5
tPHL21
85
3 V Operation
Side 1 to Side 2, Rising Edge2
tPLH12
82
Side 1 to Side 2, Falling Edge3
tPHL12
196
Side 2 to Side 1, Rising Edge4
tPLH21
32
Side 2 to Side 1, Falling Edge5
tPHL21
110
PULSE WIDTH DISTORTION
5 V Operation
Side 1 to Side 2, |tPLH12 − tPHL12|
PWD12
67
Side 2 to Side 1, |tPLH21 − tPHL21|
PWD21
54
3 V Operation
Side 1 to Side 2, |tPLH12 − tPHL12|
PWD12
114
Side 2 to Side 1, |tPLH21 − tPHL21|
PWD21
77
COMMON-MODE TRANSIENT IMMUNITY6 |CMH|, |CML| 25
35
Max
120
120
120
120
130
275
70
155
125
340
75
210
145
85
215
135
Unit Test Conditions/Comments
kHz
4.5 V ≤ VDD1, VDD2 ≤ 5.5 V, CL1 = 40 pF,
R1 = 1.6 kΩ, CL2 = 400 pF, R2 = 180 Ω
ns
ns
3.0 V ≤ VDD1, VDD2 ≤ 3.6 V, CL1 = 40 pF,
R1 = 1.0 kΩ, CL2 = 400 pF, R2 = 120 Ω
ns
ns
4.5 ≤ VDD1, VDD2 ≤ 5.5 V, CL1 = CL2 = 0 pF,
R1 = 1.6 kΩ, R2 = 180 Ω
ns
ns
ns
ns
3.0 V ≤ VDD1, VDD2 ≤ 3.6 V, CL1 = CL2 = 0 pF,
R1 = 1.0 kΩ, R2 = 120 Ω
ns
ns
ns
ns
ns
ns
ns
ns
kV/μs
4.5 V ≤ VDD1, VDD2 ≤ 5.5 V, CL1 = CL2 = 0 pF,
R1 = 1.6 kΩ, R2 = 180 Ω
3.0 V ≤ VDD1, VDD2 ≤ 3.6 V, CL1 = CL2 = 0 pF,
R1 = 1.0 kΩ, R2 = 120 Ω
1 All voltages are relative to their respective ground.
2 tPLH12 propagation delay is measured from the Side 1 input logic threshold to an output value of 0.7 VDD2.
3 tPHL12 propagation delay is measured from the Side 1 input logic threshold to an output value of 0.4 V.
4 tPLH21 propagation delay is measured from the Side 2 input logic threshold to an output value of 0.7 VDD1.
5 tPHL21 propagation delay is measured from the Side 2 input logic threshold to an output value of 0.9 V.
6 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
Rev. I | Page 4 of 16
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