ADXL313WACPZ データシートの表示（PDF） - Analog Devices

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ADXL313WACPZ

Digital Accelerometer / 32-Lead Lead Frame Chip

Analog Devices 

Data Sheet

ADXL313

INTERRUPTS

The ADXL313 provides two output pins for driving interrupts:

INT1 and INT2. Both interrupt pins are push-pull, low impedance

pins with output specifications shown in Table 12. The default

configuration of the interrupt pins is active high. This can be

changed to active low by setting the INT_INVERT bit in the

DATA_FORMAT register (Address 0x31). All functions can be

used simultaneously, with the only limiting feature being that

some functions may need to share interrupt pins.

Interrupts are enabled by setting the appropriate bit in the

INT_ENABLE register (Address 0x2E) and are mapped to either

the INT1 or INT2 pin based on the contents of the INT_MAP

register (Address 0x2F). When initially configuring the interrupt

pins, it is recommended that the functions and interrupt mapping

be completed before enabling the interrupts. When changing the

configuration of an interrupt, it is recommended that the interrupt

be disabled first, by clearing the bit corresponding to that function

in the INT_ENABLE register, and then the function be reconfig-

ured before enabling the interrupt again. Configuration of the

functions while the interrupts are disabled helps to prevent the

accidental generation of an interrupt.

The interrupt functions are latched and cleared either by reading

the data registers (Address 0x32 to Address 0x37) until the inter-

rupt condition is no longer valid for the data-related interrupts

or by reading the INT_SOURCE register (Address 0x30) for the

remaining interrupts. The following sections describe the

interrupts that can be set in the INT_ENABLE register and

monitored in the INT_SOURCE register.

DATA_READY

The DATA_READY bit is set when new data is available and is

cleared when no new data is available.

Table 12. Interrupt Pin Digital Output

Parameter

Digital Output

Low Level Output Voltage (VOL)

High Level Output Voltage (VOH)

Low Level Output Current (IOL)

High Level Output Current (IOH)

Pin Capacitance

Rise/Fall Time

Rise Time (tR)2

Fall Time (tF)3

Test Conditions/Comments

IOL = 300 µA

IOH = −150 µA

VOL = VOL, max

VOH = VOH, min

fIN = 1 MHz, VIN = 2.5 V

CLOAD = 150 pF

CLOAD = 150 pF

1 Limits based on characterization results, not production tested.

2 Rise time is measured as the transition time from VOL, max to VOH, min of the INTx pin.

3 Fall time is measured as the transition time from VOH, min to VOL, max of the INTx pin.

Activity

The activity bit is set when acceleration greater than the value

stored in the THRESH_ACT register (Address 0x24) is sensed.

Inactivity

The inactivity bit is set when acceleration of less than the value

stored in the THRESH_INACT register (Address 0x25) is sensed

for more time than is specified in the TIME_INACT register

(Address 0x26). The maximum value for TIME_INACT is 255 sec.

Watermark

The watermark bit is set when the number of samples in

the FIFO equals the value stored in the samples bits in the

FIFO_CTL register (Address 0x38). The watermark bit is

cleared automatically when the FIFO is read, and the content

returns to a value below the value stored in the samples bits.

Overrun

The overrun bit is set when new data replaces unread data. The

precise operation of the overrun function depends on the FIFO

mode. In bypass mode, the overrun bit is set when new data

replaces unread data in the DATA_Xx, DATA_Yx, and DATA_Zx

registers (Address 0x32 to Address 0x37). In all other modes, the

overrun bit is set when the FIFO is filled. The overrun bit is

automatically cleared when the contents of FIFO are read.

FIFO

The ADXL313 contains patent pending technology for an

embedded memory management system with a 32-level FIFO

that can be used to minimize host processor burden. This buffer

has four modes: bypass, FIFO, stream, and trigger (see Table 17).

Each mode is selected by the settings of the FIFO_MODE bits

in the FIFO_CTL register (Address 0x38).

Bypass Mode

In bypass mode, the FIFO is not operational and, therefore,

remains empty.

Min

0.8 × VDD I/O

300

Limit1

Max

0.2 × VDD I/O

−150

8

210

150

Unit

V

V

µA

µA

pF

ns

ns

Rev. 0 | Page 15 of 28

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