DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

MT28F002B5SG-6B データシートの表示(PDF) - Micron Technology

部品番号
コンポーネント説明
メーカー
MT28F002B5SG-6B
Micron
Micron Technology 
MT28F002B5SG-6B Datasheet PDF : 31 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
2Mb
SMART 5 BOOT BLOCK FLASH MEMORY
WRITE/ERASE CYCLE ENDURANCE
The MT28F002B5 and MT28F200B5 are designed
and fabricated to meet advanced firmware storage re-
quirements. To ensure this level of reliability, VPP must
be at 5V ±10% during WRITE or ERASE cycles. Due to
process technology advances, 5V VPP is optimal for
application and production programming. For back-
ward compatibility with SmartVoltage technology, 12V
VPP is supported for a maximum of 100 cycles and may
be connected for up to 100 cumulative hours. Opera-
tion outside these limits may reduce the number of
WRITE and ERASE cycles that can be performed on the
device.
POWER USAGE
The MT28F002B5 and MT28F200B5 offer several
power-saving features that may be utilized in the array
read mode to conserve power. Deep power-down mode
is enabled by bringing RP# LOW. Current draw (ICC) in
this mode is a maximum of 20µA at 5V VCC. When CE#
is HIGH, the device will enter standby mode. In this
mode, maximum ICC current is 130µA at 5V. If CE# is
brought HIGH during a WRITE or ERASE, the ISM will
continue to operate, and the device will consume the
respective active power until the WRITE or ERASE is
completed.
POWER-UP
The likelihood of unwanted WRITE or ERASE opera-
tions is minimized since two consecutive cycles are
required to execute either operation. However, to reset
the ISM and to provide additional protection while VCC
is ramping, one of the following conditions must be
met:
• RP# must be held LOW until VCC is at valid
functional level; or
• CE# or WE# may be held HIGH and
RP# must be toggled from VCC-GND-VCC.
After a power-up or RESET, the status register is reset,
and the device will enter the array read mode.
RP#
VCC
(5V)
,,,,,, Address
Note 1
tAA
VALID
,,
Data
NOTE:
VALID
,, tRWH
UNDEFINED
1. VCC must be within the valid operating range before RP#
goes HIGH.
Figure 2
Power-Up/Reset Timing Diagram
2Mb Smart 5 Boot Block Flash Memory
F50.p65 – Rev. 1/00
14
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]