AP2181/AP2191
1.5A SINGLE CHANNEL CURRENT-LIMITED POWER
SWITCH
Electrical Characteristics
(TA = 25°C, VIN = +5.0V, unless otherwise stated)
Symbol
Parameter
Test Conditions
Min Typ. Max Unit
VUVLO Input UVLO
Rload=1kΩ
1.6 1.9 2.5 V
ISHDN Input Shutdown Current
IQ Input Quiescent Current
Disabled, IOUT= 0
Enabled, IOUT= 0
0.5 1 μA
45 70 μA
ILEAK Input Leakage Current
Disabled, OUT grounded
1 μA
IREV Reverse Leakage Current
RDS(ON) Switch on-resistance
ISHORT Short-Circuit Current Limit
Disabled, VIN= 0V, VOUT= 5V, IREV at VIN
SOT25, MSOP-8L-EP,
VIN = 5V,
IOUT= 1.5A
TA = 25°C SOP-8L
DFN2018-6
-40°C ≤ TA ≤ 85°C
VIN = 3.3V, TA = 25°C
IOUT= 1.5A -40°C ≤ TA ≤ 85°C
Enabled into short circuit, CL=100μF
1
μA
95 115
90 110
140 mΩ
120 140
170
2.0
A
ILIMIT Over-Load Current Limit
VIN= 5V, VOUT= 4.5V, CL=120μF, -40°C≤TA ≤85°C 1.6 2.1 2.6 A
ITrig
Current limiting trigger
threshold
Output Current Slew rate (<100A/s) , CL=100μF
2.6
A
VIL
VIH
ISINK
TD(ON)
TR
TD(OFF)
TF
RFLG
TBlank
TSHDN
EN Input Logic Low Voltage VIN = 2.7V to 5.5V
EN Input Logic High Voltage VIN = 2.7V to 5.5V
EN Input leakage
VEN = 5V
Output turn-on delay time
CL=1μF, Rload=10Ω
Output turn-on rise time
CL=1μF, Rload=10Ω
Output turn-off delay time
CL=1μF, Rload=10Ω
Output turn-off fall time
CL=1μF, Rload=10Ω
FLG output FET on-resistance IFLG =10mA, CL=100μF
FLG blanking time
CIN=10uF, CL=100μF
Thermal Shutdown Threshold Enabled, Rload=1kΩ
0.8 V
2
V
1 μA
0.05
ms
0.6 1.5 ms
0.01
ms
0.05 0.1 ms
20 40 Ω
4
7 15 ms
140
°C
THYS Thermal Shutdown Hysteresis
25
°C
SOP-8L (Note 4)
110
°C/W
θJA
Thermal Resistance
Junction-to-Ambient
MSOP-8L-EP (Note 5)
SOT25 (Note 6)
60
°C/W
157
°C/W
DFN2018-6 (Note 7)
70
°C/W
Notes:
4. Test condition for SOP-8L: Device mounted on FR-4, 2oz copper, with minimum recommended pad layout.
5. Test condition for MSOP-8L-EP: Device mounted on 2” x 2” FR-4 substrate PC board, 2oz copper, with minimum recommended pad on top
layer and thermal vias to bottom layer ground plane.
6. Test condition for SOT25: Device mounted on FR-4, 2oz copper, with minimum recommended pad layout.
7. Test condition for DFN2018-6: Device mounted on FR-4 2-layer board, 2oz copper, with minimum recommended pad on top layer and 3 vias
to bottom layer 1.0”x1.4” ground plane.
AP2181/AP2191 Rev. 6
DS31563
5 of 18
www.diodes.com
JUNE 2009
© Diodes Incorporated