APL5332K データシートの表示（PDF） - Anpec Electronics

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APL5332K

CMOS LDO with Source-Sink & Output Selection Functions

Anpec Electronics 

APL5332

Application Information

Figure 3 shows a board layout using the SOP-8-P

package. The demoboard is made of FR-4 material

and is a two-layer PCB. The board size and thickness

are 65mm* 65mm and 1.6mm. The copper thickness

of top and bottom layers is 2 oz. The partial layout

around APL5332 is as the details above and shown in

the figure 2. It uses 15mil vias to connect the top and

bottom ground plane. The θJA of the APL5332 (SOP-8-

P) mounted on the demodoard is about 41.3oC/W in

free air. Assuming the TA=25oC and the maximum

TJ=150oC (typical thermal limit temperature), the maxi-

mum power dissipation is calculated as :

PD(max) = (150 - 25) / 41.3

= 3.03W

If the TJ is designed to be below 125oC, the calculated

power dissipation should be less than :

PD = (125 - 25) / 41.3

= 2.42W

APL5332

APL5332

Figure 3(b) Top layer

Figure 3(a) TopOver layer

Figure 3(c) Bottom layer

Copyright  ANPEC Electronics Corp.

11

Rev. A.3 - Oct., 2003

www.anpec.com.tw

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