C8051F044 データシートの表示（PDF） - Silicon Laboratories

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C8051F044

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

JTAG Register Definition 25.3. FLASHCON: JTAG Flash Control Register

SFLE

Bit7

WRMD2 WRMD1 WRMD0

Bit6

Bit5

Bit4

RDMD3

Bit3

RDMD2

Bit2

RDMD1

Bit1

RDMD0

Bit0

Reset Value

00000000

This register determines how the Flash interface logic will respond to reads and writes to the 

FLASHDAT Register. 

Bit 7:

Bits6-4:

Bits3-0:

SFLE: Scratchpad Flash Memory Access Enable

When this bit is set, Flash reads and writes from user software are directed to the 128-byte

scratchpad Flash sector. When accessing the scratchpad, Flash accesses out of the

address range 0x00-0x7F should not be attempted. Reads/Writes outside of this range will

yield undefined results.

0: Flash access is directed to the Program/Data Flash sector.

1: Flash access is directed to the 128-byte scratchpad sector.

WRMD2-0: Write Mode Select Bits.

The Write Mode Select Bits control how the interface logic responds to writes to the FLASH-

DAT Register per the following values:

000: A FLASHDAT write replaces the data in the FLASHDAT register, but is otherwise

ignored.

001: A FLASHDAT write initiates a write of FLASHDAT into the memory address by the

FLASHADR register. FLASHADR is incremented by one when complete.

010: A FLASHDAT write initiates an erasure (sets all bytes to 0xFF) of the Flash page

containing the address in FLASHADR. The data written must be 0xA5 for the erase

to occur. FLASHADR is not affected. If FLASHADR targets the Read Lock Byte or

the Write/Erase Lock Byte, the entire user space will be erased (i.e. entire Flash

memory except for the Reserved area (See Section “15. Flash Memory” on

page 179).

(All other values for WRMD2-0 are reserved.)

RDMD3-0: Read Mode Select Bits.

The Read Mode Select Bits control how the interface logic responds to reads to the FLASH-

DAT Register per the following values:

0000: A FLASHDAT read provides the data in the FLASHDAT register, but is otherwise

ignored.

0001: A FLASHDAT read initiates a read of the byte addressed by the FLASHADR regis-

ter if no operation is currently active. This mode is used for block reads.

0010: A FLASHDAT read initiates a read of the byte addressed by FLASHADR only if no

operation is active and any data from a previous read has already been read from

FLASHDAT. This mode allows single bytes to be read (or the last byte of a block)

without initiating an extra read.

(All other values for RDMD3-0 are reserved.)

322

Rev. 1.5

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