CS8415A-CSZR データシートの表示（PDF） - Cirrus Logic
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CS8415A-CSZR Datasheet PDF : 46 Pages
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CS8415A
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE
Inputs: Logic 0 = 0 V, Logic 1 = VL+; CL = 20 pF.
Parameter
CCLK Clock Frequency
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
CCLK Falling to CDOUT Stable
Rise Time of CDOUT
Fall Time of CDOUT
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
Symbol Min Typ Max
(Note 12)
fsck
0
-
6.0
tcsh
1.0
-
-
tcss
20
-
-
tscl
66
-
-
tsch
66
-
-
tdsu
40
-
-
(Note 13)
tdh
15
-
-
tpd
-
-
50
tr1
-
-
25
tf1
-
-
25
(Note 14)
tr2
-
-
100
(Note 14)
tf2
-
-
100
Units
MHz
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12. If Fs is lower than 46.875 kHz, the maximum CCLK frequency should be less than 128 Fs. This is dic-
tated by the timing requirements necessary to access the Channel Status and User Bit buffer memory.
Access to the control register file can be carried out at the full 6 MHz rate. The minimum allowable input
sample rate is 8 kHz, so choosing CCLK to be less than or equal to 1.024 MHz should be safe for all
possible conditions.
13. Data must be held for sufficient time to bridge the transition time of CCLK.
14. For fsck <1 MHz.
CS
t css
t scl t sch
t csh
CCLK
t r2
t f2
CDIN
CDOUT
t dsu
t dh
t pd
Figure 3. SPI Mode Timing
DS470F4
9
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