CY7C057 データシートの表示（PDF） - Cypress Semiconductor

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CY7C057

3.3V 16K/32K x 36 FLEx36™ Asynchronous Dual-Port Static RAM

Cypress Semiconductor 

CY7C056V

CY7C057V

Switching Waveforms (continued)

Timing Diagram of Write with BUSY (M/S=HIGH)[40]

ADDRESSR

R/WR

tWC

MATCH

tPWE

DATA INR

tPS

ADDRESSL

BUSYL

DATAOUTL

MATCH

tBLA

tSD

tHD

VALID

tDDD

tBHA

tBDD

tWDD

VALID

Write Timing with Busy Input (M/S=LOW)

R/W

tWB

BUSY

tPWE

tWH

Note:

40. CE0L = CE0R = LOW; CE1L = CE1R = HIGH.

Document #: 38-06055 Rev. **

Page 14 of 23

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