CY7C1325G-133BGC(2004) データシートの表示（PDF） - Cypress Semiconductor

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CY7C1325G-133BGC
(Rev.:2004)

4-Mbit (256K x 18) Flow-Through Sync SRAM

Cypress Semiconductor 

Timing Diagrams (continued)

Write Cycle Timing[16, 17]

tCYC

PRELIMINARY

CY7C1325G

CLK

ADSP

ADSC

ADDRESS

BWE,

BW[A:B]

GW

CE

ADV

t

CH

t

CL

tADS tADH

tADS tADH

tAS tAH

A1

A2

Byte write signals are ignored for first cycle when

ADSP initiates burst

tCES tCEH

t

t

WES WEH

ADSC extends burst

tADS tADH

A3

tWES tWEH

ADV suspends burst

tADVS tADVH

OE

Data in (D)

Data Out (Q)

tDS t DH

High-Z

D(A1)

tOEHZ

BURST READ

Single WRITE

D(A2)

D(A2 + 1)

D(A2 + 1)

D(A2 + 2)

D(A2 + 3)

D(A3)

D(A3 + 1)

D(A3 + 2)

BURST WRITE

DON’T CARE

UNDEFINED

Extended BURST WRITE

Document #: 38-05518 Rev. *A

Page 11 of 16

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