CY7C1327G-225BGXC データシートの表示（PDF） - Cypress Semiconductor

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CY7C1327G-225BGXC

4-Mbit (256K x 18) Pipelined Sync SRAM

Cypress Semiconductor 

Switching Waveforms

Read Cycle Timing[16]

tCYC

PRELIMINARY

CY7C1327G

CLK

ADSP

ADSC

ADDRESS

GW, BWE,

BW[A:B]

CE

ADV

OE

Data Out (Q)

tCH tCL

t

ADS

tADH

tADS tADH

tAS tAH

A1

A2

tWES tWEH

A3

Burst continued with

new base address

tCES tCEH

tADVS tADVH

Deselect

cycle

tCLZ

High-Z

tCO

tOEHZ

Q(A1)

Single READ

ADV

suspends

burst.

tOEV

tCO

tOELZ

tDOH

Q(A2) Q(A2 + 1)

Q(A2 + 2)

Q(A2 + 3)

BURST READ

tCHZ

Q(A2) Q(A2 + 1)

Burst wraps around

to its initial state

DON’T CARE UNDEFINED

Notes:

16. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

17. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:B] LOW.

Document #: 38-05519 Rev. *A

Page 11 of 18

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