CY7C1345F データシートの表示（PDF） - Cypress Semiconductor
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CY7C1345F Datasheet PDF : 17 Pages
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CY7C1345F
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
tZZREC
tZZI
tRZZI
Description
Snooze mode standby current
Device operation to ZZ
ZZ recovery time
ZZ Active to snooze current
ZZ Inactive to exit snooze current
Test Conditions
Min.
Max.
Unit
ZZ > VDD – 0.2V
40
mA
ZZ > VDD – 0.2V
2tCYC
ns
ZZ < 0.2V
2tCYC
ns
This parameter is sampled
2tCYC
ns
This parameter is sampled
0
ns
Truth Table[2, 3, 4, 5, 6]
Cycle Description
Deselected Cycle,
Power-down
Address
Used
None
CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE
HX XL
X
L
X
X
X
CLK DQ
L-H three-state
Deselected Cycle,
Power-down
None
L L XL
L
X
X
X
X L-H three-state
Deselected Cycle,
Power-down
None
L X HL
L
X
X
X
X L-H three-state
Deselected Cycle,
Power-down
None
L L XL H
L
X
X
X L-H three-state
Deselected Cycle,
Power-down
None
XX XL H
L
X
X
X L-H three-state
Snooze Mode, Power-down None
X X XH X
X
X
X
X X three-state
Read Cycle, Begin Burst
External L H L L
L
X
X
X
L L-H Q
Read Cycle, Begin Burst
External L H L L
L
X
X
X
H L-H three-state
Write Cycle, Begin Burst
External L H L L H
L
X
L
X L-H D
Read Cycle, Begin Burst
External L H L L H
L
X
H
L L-H Q
Read Cycle, Begin Burst
External L H L L H
L
X
H
H L-H three-state
Read Cycle, Continue Burst Next
XXXL H
H
L
H
L L-H Q
Read Cycle, Continue Burst Next
XX XL H
H
L
H
H L-H three-state
Read Cycle, Continue Burst Next
H X XL
X
H
L
H
L L-H Q
Read Cycle, Continue Burst Next
HX XL
X
H
L
H
H L-H three-state
Write Cycle, Continue Burst Next
XX XL H
H
L
L
X L-H D
Write Cycle, Continue Burst Next
H X XL
X
H
L
L
X L-H D
Read Cycle, Suspend Burst Current X X X L H
H
H
H
L L-H Q
Read Cycle, Suspend Burst Current X X X L H
H
H
H
H L-H three-state
Read Cycle, Suspend Burst Current H X X L
X
H
H
H
L L-H Q
Read Cycle, Suspend Burst Current H X X L
X
H
H
H
H L-H three-state
Write Cycle, Suspend Burst Current X X X L H
H
H
L
X L-H D
Write Cycle, Suspend Burst Current H X X L
X
H
H
L
X L-H D
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW= L. WRITE = H when all Byte write enable signals
(BWA, BWB, BWC, BWD), BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A: D]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is
a don't care for the remainder of the write cycle.
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are three-state when OE
is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05214 Rev. *C
Page 6 of 17
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