CY8C3665PVI-008(2010) データシートの表示（PDF） - Cypress Semiconductor

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CY8C3665PVI-008
(Rev.:2010)

Programmable System-on-Chip (PSoC®)

Cypress Semiconductor 

PRELIMINARY

PSoC® 3: CY8C36 Family Datasheet

5.6.3 SFRs

The special function register (SFR) space provides access to frequently accessed registers. The memory map for the SFR memory

space is shown in Table 5-2.

Table 5-2. SFR Map

Address

0/8

1/9

2/A

3/B

4/C

5/D

6/E

7/F

0×F8 SFRPRT15DR SFRPRT15PS SFRPRT15SEL –

–

–

–

–

0×F0 B

–

SFRPRT12SEL –

–

–

–

–

0×E8 SFRPRT12DR SFRPRT12PS MXAX

–

–

–

–

–

0×E0 ACC

–

–

–

–

–

–

–

0×D8 SFRPRT6DR SFRPRT6PS SFRPRT6SEL –

–

–

–

–

0×D0 PSW

–

–

–

–

–

–

–

0×C8 SFRPRT5DR SFRPRT5PS SFRPRT5SEL –

–

–

–

–

0×C0 SFRPRT4DR SFRPRT4PS SFRPRT4SEL –

–

–

–

–

0×B8 –

–

–

–

–

–

–

–

0×B0 SFRPRT3DR SFRPRT3PS SFRPRT3SEL –

–

–

–

–

0×A8 IE

–

–

–

–

–

–

–

0×A0 P2AX

–

SFRPRT1SEL –

–

–

–

–

0×98 SFRPRT2DR SFRPRT2PS SFRPRT2SEL –

–

–

–

–

0×90 SFRPRT1DR SFRPRT1PS –

DPX0

–

DPX1

–

–

0×88 –

SFRPRT0PS SFRPRT0SEL –

–

–

–

–

0×80 SFRPRT0DR SP

DPL0

DPH0

DPL1

DPH1

DPS

–

The CY8C36 family provides the standard set of registers found

on industry standard 8051 devices. In addition, the CY8C36

devices add SFRs to provide direct access to the I/O ports on the

device. The following sections describe the SFRs added to the

CY8C36 family.

XData Space Access SFRs

The 8051 core features dual DPTR registers for faster data

transfer operations. The data pointer select SFR, DPS, selects

which data pointer register, DPTR0 or DPTR1, is used for the

following instructions:

„ MOVX @DPTR, A

„ MOVX A, @DPTR

„ MOVC A, @A+DPTR

„ JMP @A+DPTR

„ INC DPTR

„ MOV DPTR, #data16

The extended data pointer SFRs, DPX0, DPX1, MXAX, and

P2AX, hold the most significant parts of memory addresses

during access to the xdata space. These SFRs are used only

with the MOVX instructions.

During a MOVX instruction using the DPTR0/DPTR1 register,

the most significant byte of the address is always equal to the

contents of DPX0/DPX1.

During a MOVX instruction using the R0 or R1 register, the most

significant byte of the address is always equal to the contents of

MXAX, and the next most significant byte is always equal to the

contents of P2AX.

I/O Port SFRs

The I/O ports provide digital input sensing, output drive, pin

interrupts, connectivity for analog inputs and outputs, LCD, and

access to peripherals through the DSI. Full information on I/O

ports is found in I/O System and Routing on page 28.

I/O ports are linked to the CPU through the PHUB and are also

available in the SFRs. Using the SFRs allows faster access to a

limited set of I/O port registers, while using the PHUB allows boot

configuration and access to all I/O port registers.

Each SFR supported I/O port provides three SFRs:

„ SFRPRTxDR sets the output data state of the port (where × is

port number and includes ports 0–6, 12 and 15).

„ The SFRPRTxSEL selects whether the PHUB PRTxDR

register or the SFRPRTxDR controls each pin’s output buffer

within the port. If a SFRPRTxSEL[y] bit is high, the

corresponding SFRPRTxDR[y] bit sets the output state for that

pin. If a SFRPRTxSEL[y] bit is low, the corresponding

PRTxDR[y] bit sets the output state of the pin (where y varies

from 0 to 7).

„ The SFRPRTxPS is a read only register that contains pin state

values of the port pins.

Document Number: 001-53413 Rev. *I

Page 20 of 112

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