CY8C3665PVI-008(2010) データシートの表示（PDF） - Cypress Semiconductor
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CY8C3665PVI-008 Datasheet PDF : 112 Pages
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PRELIMINARY
PSoC® 3: CY8C36 Family Datasheet
Figure 2-3. 68-pin QFN Part Pinout[10]
(GPIO) P2[6] 1
(GPIO) P2[7] 2
(I2C0: SCL, SIO) P12[4] 3
(I2C0: SDA, SIO) P12[5] 4
Vssb 5
Ind 6
Vboost 7
Vbat 8
Vssd 9
XRES 10
(TMS, SWDIO, GPIO) P1[0] 11
(TCK, SWDCK, GPIO) P1[1] 12
(configurable XRES, GPIO) P1[2] 13
(TDO, SWV, GPIO) P1[3] 14
(TDI, GPIO) P1[4] 15
(nTRST, GPIO) P1[5] 16
Vddio1 17
Lines show Vddio
to I/O supply
association
QFN
(Top View)
51 P0[3] (GPIO, OpAmp0-/Extref0)
50 P0[2] (GPIO, OpAmp0+)
49 P0[1] (GPIO, OpAmp0out)
48 P0[0] (GPIO, OpAmp2out)
47 P12[3] (SIO)
46 P12[2] (SIO)
45 Vssd
44 Vdda
43 Vssa
42 Vcca
41 P15[3] (GPIO, kHz XTAL: Xi)
40 P15[2] (GPIO, kHz XTAL: Xo)
39 P12[1] (SIO, I2C1: SDA)
38 P12[0] (SIO, 12C1: SCL) [9]
37 P3[7] (GPIO, OpAmp3out) [9]
36 P3[6] (GPIO, OpAmp1out)
35 Vddio3
Notes
8. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
9. This feature on select devices only. See Ordering Information on page 100 for details.
10. The center pad on the QFN package should be connected to digital ground (Vssd) for best mechanical, thermal, and electrical performance. If not connected to ground,
it should be electrically floated and not connected to any other signal.
Document Number: 001-53413 Rev. *I
Page 7 of 112
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