MT48LC128M4A2P データシートの表示（PDF） - Micron Technology

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コンポーネント説明

メーカー

MT48LC128M4A2P

Synchronous DRAM

Micron Technology 

512Mb: x4, x8, x16 SDRAM

Register Definition

Figure 5:

Mode Register Definition

A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus

12 11 10 9 8 7

Reserved1 WB Op Mode

6 543

CAS Latency BT

2 10

Burst Length

Mode Register (Mx)

M9

Write Burst Mode

0

Programmed burst length

1

Single location access

M8

M7

M6-M0

Operating Mode

0

0

Defined Standard operation

–

–

–

All other states reserved

M6 M5 M4

0 00

0 01

0 10

0 11

1 00

1 01

1 10

1 11

CAS Latency

Reserved

Reserved

2

3

Reserved

Reserved

Reserved

Reserved

M2 M1 M0

0 00

0 01

0 10

0 11

1 00

1 01

1 10

1 11

Burst Length

M3 = 0

1

2

4

8

Reserved

Reserved

Reserved

Full Page

M3 = 1

1

2

4

8

Reserved

Reserved

Reserved

Reserved

M3

Burst Type

0

Sequential

1

Interleaved

Notes: 1. Should program M12, M11, M10 = “0, 0, 0” to ensure compatibility with future devices.

PDF: 09005aef809bf8f3/Source: 09005aef80818a4a

512MbSDRAM.fm - Rev. L 10/07 EN

14

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2000 Micron Technology, Inc. All rights reserved.

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