DS1856 データシートの表示（PDF） - Maxim Integrated
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DS1856 Datasheet PDF : 31 Pages
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Dual, Temperature-Controlled Resistors with Inter-
nally Calibrated Monitors and Password Protection
AC ELECTRICAL CHARACTERISTICS
(VCC = 2.85V to 5.5V, TA = -40°C to +95°C, unless otherwise noted. See Figure 6.)
PARAMETER
SCL Clock Frequency (Note 9)
Bus Free Time Between STOP and
START Condition (Note 9)
Hold Time (Repeated)
START Condition (Notes 9, 10)
LOW Period of SCL Clock (Note 9)
HIGH Period of SCL Clock (Note 9)
Data Hold Time (Notes 9, 11, 12)
Data Setup Time (Note 9)
START Setup Time (Note 9)
Rise Time of Both SDA and SCL
Signals (Note 13)
Fall Time of Both SDA and SCL
Signals (Note 13)
Setup Time for STOP Condition
Capacitive Load for Each Bus Line
EEPROM Write Time
SYMBOL
CONDITIONS
Fast mode
fSCL
Standard mode
Fast mode
tBUF
Standard mode
Fast mode
tHD:STA Standard mode
tLOW
Fast mode
Standard mode
tHIGH
Fast mode
Standard mode
Fast mode
tHD:DAT Standard mode
Fast mode
tSU:DAT Standard mode
Fast mode
tSU:STA Standard mode
Fast mode
tR
Standard mode
Fast mode
tF
Standard mode
Fast mode
tSU:STO
Standard mode
CB (Note 13)
tW
MIN TYP
0
0
1.3
4.7
0.6
4.0
1.3
4.7
0.6
4.0
0
0
100
250
0.6
4.7
20 + 0.1CB
20 + 0.1CB
20 + 0.1CB
20 + 0.1CB
0.6
4.0
10
MAX
400
100
UNITS
kHz
µs
µs
µs
µs
0.9
µs
ns
µs
300
ns
1000
300
ns
300
µs
400
pF
20
ms
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
All voltages are referenced to ground.
I/O pins of fast-mode devices must not obstruct the SDA and SCL lines if VCC is switched off.
SDA and SCL are connected to VCC and all other input signals are connected to well-defined logic levels.
Full scale is user programmable. The maximum voltage that the MON inputs read is approximately full scale, even if the volt-
age on the inputs is greater than full scale.
This voltage defines the maximum range of the analog-to-digital converter voltage, not the maximum VCC voltage.
Absolute linearity is the difference of measured value from expected value at DAC position. The expected value is a
straight line from measured minimum position to measured maximum position.
Relative linearity is the deviation of an LSB DAC setting change vs. the expected LSB change. The expected LSB change
is the slope of the straight line from measured minimum position to measured maximum position.
See the Typical Operating Characteristics.
A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT > 250ns must then be met. This
is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the
LOW period of the SCL signal, it must output the next data bit to the SDA line tRMAX + tSU:DAT = 1000ns + 250ns = 1250ns
before the SCL line is released.
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