DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

DS3251N データシートの表示(PDF) - Dallas Semiconductor -> Maxim Integrated

部品番号
コンポーネント説明
メーカー
DS3251N
Dallas
Dallas Semiconductor -> Maxim Integrated 
DS3251N Datasheet PDF : 71 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
DS3251/DS3252/DS3253/DS3254
TABLE OF CONTENTS
1. STANDARDS COMPLIANCE ......................................................................................................... 6
2. DETAILED DESCRIPTION ............................................................................................................. 7
3. APPLICATION EXAMPLE .............................................................................................................. 7
4. BLOCK DIAGRAMS........................................................................................................................ 8
5. CONTROL INTERFACE MODES.................................................................................................... 9
6. PIN DESCRIPTIONS ..................................................................................................................... 10
7. REGISTER DESCRIPTIONS......................................................................................................... 15
8. RECEIVER .................................................................................................................................... 24
8.1 INTERFACING TO THE LINE........................................................................................................................... 24
8.2 OPTIONAL PREAMP ..................................................................................................................................... 24
8.3 AUTOMATIC GAIN CONTROL (AGC) AND ADAPTIVE EQUALIZER..................................................................... 24
8.4 CLOCK AND DATA RECOVERY (CDR)........................................................................................................... 24
8.5 LOSS-OF-SIGNAL (LOS) DETECTOR ............................................................................................................ 24
8.6 FRAMER INTERFACE FORMAT AND THE B3ZS/HDB3 DECODER .................................................................... 25
8.7 RECEIVE LINE-CODE VIOLATION COUNTER .................................................................................................. 26
8.8 RECEIVER POWER-DOWN ........................................................................................................................... 26
8.9 RECEIVER JITTER TOLERANCE .................................................................................................................... 26
9. TRANSMITTER ............................................................................................................................. 27
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
10.
TRANSMIT CLOCK ....................................................................................................................................... 27
FRAMER INTERFACE FORMAT AND THE B3ZS/HDB3 ENCODER .................................................................... 27
PATTERN GENERATION ............................................................................................................................... 27
WAVESHAPING, LINE BUILD-OUT, LINE DRIVER............................................................................................ 28
INTERFACING TO THE LINE........................................................................................................................... 28
TRANSMIT DRIVER MONITOR ....................................................................................................................... 28
TRANSMITTER POWER-DOWN...................................................................................................................... 28
TRANSMITTER JITTER GENERATION (INTRINSIC) ........................................................................................... 28
TRANSMITTER JITTER TRANSFER................................................................................................................. 28
JITTER ATTENUATOR ............................................................................................................. 32
11. DIAGNOSTICS .......................................................................................................................... 34
11.1 PRBS GENERATOR AND DETECTOR............................................................................................................ 34
11.2 LOOPBACKS ............................................................................................................................................... 34
12. CLOCK ADAPTER.................................................................................................................... 35
13. RESET LOGIC .......................................................................................................................... 35
14. TRANSFORMERS..................................................................................................................... 36
15. CPU INTERFACES ................................................................................................................... 37
15.1 PARALLEL INTERFACE ................................................................................................................................. 37
15.2 SPI INTERFACE .......................................................................................................................................... 37
16. JTAG TEST ACCESS PORT AND BOUNDARY SCAN............................................................ 40
16.1 JTAG DESCRIPTION ................................................................................................................................... 40
16.2 JTAG TAP CONTROLLER STATE MACHINE DESCRIPTION............................................................................. 40
16.3 JTAG INSTRUCTION REGISTER AND INSTRUCTIONS...................................................................................... 42
16.4 JTAG TEST REGISTERS.............................................................................................................................. 43
17. ELECTRICAL CHARACTERISTICS ......................................................................................... 44
18. PIN ASSIGNMENTS.................................................................................................................. 56
19. PACKAGE INFORMATION....................................................................................................... 70
20. THERMAL INFORMATION ....................................................................................................... 71
21. REVISION HISTORY................................................................................................................. 71
2 of 71

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]