LTC1282(Rev0) データシートの表示（PDF） - Linear Technology

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LTC1282
(Rev.:Rev0)

3V 140ksps 12-Bit Sampling A/D Converter with Reference

Linear Technology 

LTC1282

APPLICATI S I FOR ATIO

CS

RD

BUSY

DATA

HOLD

TRACK

t1

t4

t5

t2

t CONV

t3

t7

OLD DATA

DB11-DB0

t12

t1

t4

t11

t2

t5

t CONV

t3

t7

NEW DATA

DB11-DB0

t12

LTC1282 • F18

Figure 18. ROM Mode, Parallel Read Timing Diagram (HBEN = LOW)

Table 4. ROM Mode, Parallel Read Data Bus Status

Data Outputs

First Read (Old Data)

Second Read

D11 D10

D9

D8

D7

D6

D5

D4 D3/11 D2/10 D1/9 D0/8

DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

ROM Mode, Parallel Read (HBEN = LOW)

The ROM Mode avoids placing a microprocessor into a

WAIT state. A conversion is started with a READ operation,

and the 12 bits of data from the previous conversion are

available on data outputs D11...D0/8 (see Figure 18 and

Table 4). This data may be disregarded if not required. A

second READ operation reads the new data (DB11...DB0)

and starts another conversion. A delay at least as long as

the ADC’s conversion time plus the 1.0µs minimum delay

between conversions must be allowed between READ

operations.

ROM Mode, Two Byte Read

As previously mentioned for a two byte read, only data

outputs D7...D0/8 are used. Conversion is started in the

normal way with a READ operation and the data output

status is the same as the ROM mode, Parallel Read (see

Figure 19 timing diagram and Table 5 data bus status).

Two more READ operations are required to access the new

conversion result. A delay equal to the ADC’s conversion

time must be allowed between conversion start and the

second data READ operation. The second READ operation

with HBEN high disables conversion start and places the

high byte (4MSBs) on data outputs D3/11...D0/8. A third

read operation accesses the low data byte (DB7...DB0)

and starts another conversion. The 4MSBs appear on data

outputs D11...D8 during all three read operations.

MICROPROCESSOR INTERFACING

The LTC1282 allows easy interfacing to digital signal

processors as well as modern high speed, 8-bit or 16-

bit microprocessors. Here are several examples.

TMS320C25

Figure 20 shows an interface between the LTC1282 and

the TMS320C25.

The R/W signal of the DSP initiates a conversion and

conversion results are read from the LTC1282 using the

following instruction:

IN D, PA

18

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