FAN5018BMTC データシートの表示（PDF） - Fairchild Semiconductor

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FAN5018BMTC

6-Bit VID Controller 2-4 Phase VR10.X Controller

Fairchild Semiconductor 

PRODUCT SPECIFICATION

FAN5018B

Typically, for main MOSFETs, one wants the highest

speed (low CISS) device, but these usually have higher

ON-resistance. Select a device that meets the total power

dissipation (about 1.5 W for a single D-PAK) when combin-

ing the switching and conduction losses.

For our example, we have selected a Fairchild FD6696 as the

main MOSFET (three total; nMF = 3), with a Ciss = 2058 pF

(max) and RDS(MF) = 15m (max at TJ = 125ºC) and a

Fairchild FDD6682 as the synchronous MOSFET (six total;

nSF = 6), with Ciss = 2880pF (max) and RDS(SF) = 11.9mΩ

(max at TJ = 125ºC). The synchronous MOSFET Ciss is less

than 3000 pF, satisfying that requirement. Solving for the

power dissipation per MOSFET at IO = 65A and IR = 8.86A

yields 1.24W for each synchronous MOSFET and 1.62W for

each main MOSFET. These numbers work well considering

there is usually more PCB area available for each main

MOSFET versus each synchronous MOSFET.

One last item to look at is the power dissipation in the driver

for each phase. This is best described in terms of the QG for

the MOSFETs and is given by the following, where QGMF is

the total gate charge for each main MOSFET and QGSF is the

total gate charge for each synchronous MOSFET:

( ) PDRV

=

⎡ fSW

⎢⎣ 2 × n

×

nMF × QGMF + nSF × QGSF

+

I

CC

⎤

⎥⎦

×VCC

(18)

Also shown is the standby dissipation factor (ICC times the

VCC) for the driver. For the FAN5009, the maximum dissipa-

tion should be less than 400 mW. For our example, with

ICC = 7 mA, QGMF = 24nC (max) and QGSF = 31nC (max),

we find 202 mW in each driver, which is below the 400 mW

dissipation limit. See the FAN5009 data sheet for more

details.

Ramp Resistor Selection

The ramp resistor (RR) is used for setting the size of the

internal PWM ramp. This resistor’s value is chosen to pro-

vide the best combination of thermal balance, stability, and

transient response. The following expression is used for

determining the optimum value:

RR

=

3×

AR

AD ×

×L

RDS

× CR

(19)

RR

=

0.2 × 650nH

3× 5 × 5.95mΩ × 5 pF

=

291kΩ

where AR is the internal ramp amplifier gain, AD is the

current balancing amplifier gain, RDS is the total low-side

MOSFET ON-resistance, and CR is the internal ramp

capacitor value. A close standard 1% resistor value is 301kΩ.

The internal ramp voltage magnitude can be calculated

using:

VR

=

AR × (1− D)×VVID

RR × CR × fSW

(20)

VR

=

0.2 × (1− 0.125)×1.5V

301kΩ × 5 pF × 228kHz

=

0.765V

The size of the internal ramp can be made larger or smaller.

If it is made larger, stability and transient response will

improve, but thermal balance will degrade. Likewise, if the

ramp is made smaller, thermal balance will improve at the

sacrifice of transient response and stability. The factor of

three in the denominator of equation 19 sets a ramp size that

gives an optimal balance for good stability, transient

response, and thermal balance.

COMP Pin Ramp

There is a ramp signal on the COMP pin due to the droop

voltage and output voltage ramps. This ramp amplitude adds

to the internal ramp to produce the following overall ramp

signal at the PWM input.

VRT

=

⎜⎜⎝⎛1 −

VR

2 × (1− n × D)

n × f SW × CX × RO

⎟⎟⎠⎞

(21)

For this example, the overall ramp signal is found to be

0.974V.

Current Limit Set Point

To select the current limit set point, we need to find the

resistor value for RLIM. The current limit threshold for the

FAN5018B is set with a 3V source (VLIM) across RLIM with

a gain of 10.4mV/mA (ALIM). RLIM can be found using the

following:

RLIM

=

ALIM ×VLIM

I LIM × RO

(22)

For RLIM values greater than 500kΩ, the current limit may be

lower than expected, so some adjustment of RLIM may be

needed. Here, ILIM is the average current limit for the output

of the supply. For our example, choosing 120A for ILIM, we

find RLIM to be 200kΩ, for which we chose 200kΩ as the

nearest 1% value.

The per phase current limit described earlier has its limit

determined by the following:

I PHLIM

≅ VCOMP(MAX ) − VR − VBIAS

AD × RDS (MAX )

− IR

2

(23)

For the FAN5018B, the maximum COMP voltage

(VCOMP(MAX)) is 3.3 V, the COMP pin bias voltage (VBIAS)

is 1.2V, and the current balancing amplifier gain (AD) is 5.

Using VR of 0.765V, and RDS(MAX) of 5.95mΩ (low-side

ON-resistance at 125°C), we find a per-phase limit of 40.44A.

REV. 1.0.0 Jul/15/05

23

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