H5DU2562GFR-XXC データシートの表示（PDF） - Hynix Semiconductor

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H5DU2562GFR-XXC

256Mb DDR SDRAM

Hynix Semiconductor 

H5DU2562GFR

Power-Up Sequence

VDD

VDDQ

VTT

VREF

/CLK

CLK

tVTD

CKE

CMD

LVCMOS Low Level

tIS tIH

NOP

PRE

EMRS

MRS

NOP

PRE

AREF

MRS

ACT

RD

DM

ADDR

CODE

CODE

CODE

CODE

CODE

A10

CODE

CODE

CODE

CODE

CODE

BA0, BA1

DQS

DQ'S

CODE

CODE

CODE

CODE

CODE

T=200usec

Power UP

VDD and CK stable

tRP

tMRD

tMRD

tRP

tRFC

tMRD

Precharge All

EMRS Set MRS Set

Reset DLL

(with A8=H)

tXSRD*

Precharge All 2 or more

MRS Set

Auto Refresh (with A8=L)

Non-Read

Command

READ

* 200 cycle(tXSRD) of CK are required (for DLL locking) before Read Command

Rev. 1.1 /Sep. 2007

11

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