HIP4086AP データシートの表示（PDF） - Intersil

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HIP4086AP

80V, 0.5A Three Phase Driver

Intersil 

Timing Diagrams

LOWER

TURN-OFF

XLI

XHI

XLO

XHO

XLO (RDEL = VSS)

XHO (RDEL = VSS)

UPPER

TURN-ON

HIP4086

LOWER

TURN-ON

DEAD TIME

UPPER

TURN-OFF

FIGURE 1.

DEAD TIME

DISABLE TO LOWER

TURN-ON PROP DELAY

DIS OR UV

REFRESH

PULSE WIDTH

DISABLE TURN-OFF

PROP DELAY (UPPERS)

XHI, XLI

XLO

XHO

DISABLE TO UPPER

ENABLE

NOTES:

FIGURE 2. DISABLE FUNCTION

4. X means any “A”, “B”, or “C” phase.

5. With RDEL resistor tied to VDD, lowers and uppers cannot be turned on at the same time. Low side logic overrides high side logic unless RDEL

< 100mV.

6

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