HSP50214AVI データシートの表示（PDF） - Intersil

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HSP50214AVI

Programmable Downconverter

Intersil 

AGCGNSEL

PROCCLK

CLKIN

GAINADJ(2:0)

ENI

TO OUTPUT FORMATTER

AND MICROPROCESSOR

INTERFACE

AGCOUT

A

IN(13:0)

LEVEL

DETECT

TO

µPROCESSOR

INTERFACE

MIXER

5TH ORDER

CIC

DECIMATE

FROM 4-32

0 TO 5 HALFBAND FILTER;

DECIMATION UP TO 32

(CO = 1;

Cn = 0)

255-TAP

PROGRAMMABLE

FIR FILTER

(DECIMATE UP TO 16)

AGC

LIMIT

LOOP

FILTER

ERROR

DETECT

CARTESIAN

TO

POLAR

I

RE-SAMPLER

INTERPOLATE

BY 2/4

HALFBAND

FILTERS

I2 + Q2

atan





Q--I--

Q

COF

COFSYNC

NCO

(CARRIER TRACKING)

SOF

SOFSYNC

REFCLK

MICROPROCESSOR

READ/WRITE

RD

WR

A(2:0)

C(7:0)

CONTROL

SECTION

(CO = 1;

Cn = 0)

(SYMBOL TRACKING)

NCO

OUTPUT SECTION

DISCRIMINATOR SECTION

INPUT SECTION

LEVEL DETECT SECTION

SYNCHRONIZATION SECTION

CARRIER NCO SECTIONS

CIC, HALFBAND FILTER, AND FIR SECTIONS

DIGITAL AGC SECTION

RE-SAMPLER/INTERPOLATION HALFBAND SECTION

TIMING NCO

DISCRIMINATOR

63-TAP

dθ PROGRAMMABLE

dt

FIR FILTER

DIFFERENCE

CLKIN

PROCCLK

TIMING ERROR

AGCOUT

A

CHIP

SYNCHRONIZATION

CIRCUITRY

BACK END

SYNCHRONIZATION

CIRCUITRY

FRONT END

SYNCHRONIZATION

CIRCUITRY

FIGURE 1. FUNCTIONAL BLOCK DIAGRAM OF THE HSP50214A PROGRAMMABLE DOWNCONVERTER

DATARDY

INTRRP

AOUT(15:0)

BOUT(15:0)

OEAH

OEAL

OEBH

OEBL

INTRRP

SEL(2:0)

SEROUTA

SEROUTB

SERCLK

SERSYNC

SEROE

MSYNCI

SYNCOUT

MSYNCO

SYNCIN2

SYNCIN1

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