IDT70V09L(2013) データシートの表示（PDF） - Integrated Device Technology
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IDT70V09L Datasheet PDF : 17 Pages
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HIGH-SPEED 3.3V
128K x 8 DUAL-PORT
STATIC RAM
IDT70V09L
Features
◆ True Dual-Ported memory cells which allow simultaneous
access of the same memory location
◆ High-speed access
– Commercial: 15/20ns (max.)
– Industrial: 20ns (max.)
◆ Low-power operation
– IDT70V09L
Active: 440mW (typ.)
Standby: 660µW (typ.)
◆ Dual chip enables allow for depth expansion without
external logic
◆ IDT70V09 easily expands data bus width to 16 bits or
more using the Master/Slave select when cascading more
than one device
Functional Block Diagram
R/W L
CE0L
CE1L
OEL
◆ M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
◆ Busy and Interrupt Flags
◆ On-chip port arbitration logic
◆ Full on-chip hardware support of semaphore signaling
between ports
◆ Fully asynchronous operation from either port
◆ LVTTL-compatible, single 3.3V (±0.3V) power supply
◆ Available in a 100-pin TQFP
◆ Industrial temperature range (–40°C to +85°C) is available
for selected speeds
◆ Green parts available, see ordering information
R/WR
CE0R
CE1R
OER
I/O 0-7L
I/O
Control
I/O
Control
BUSY
(1,2)
L
A16L
A0L
Address
Decoder
17
CE 0L
CE1L
OE L
R/W L
128Kx8
MEMORY
ARRAY
70V09
17
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
SEM L
INT
(2)
L
(1)
M/S
NOTES:
1. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
1
©2013 Integrated Device Technology, Inc.
Address
Decoder
I/O 0-7R
BUSY R(1,2)
A16R
A 0R
CE0R
CE1R
OER
R/WR
4852 drw 01
SEMR
INT R(2)
FEBRUARY 2013
DSC-4852/6
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